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s3c852b/P852B 8-bit cmos microcontrollers user's manual revision 0
important notice information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. this publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of samsung or others. samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including " typicals" must be validated for each customer application by the customer's technical experts. samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the samsung product could create a situation where personal injury or death may occur. should the buyer purchase or use a samsung product for any such unintended or unauthorized application, the buyer shall indemnify and hold samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that samsung was negligent regarding the design or manufacture of said product. s3c852b/P852B 8-bit cmos microcontrollers user's manual, revision 0 publication number: 20-s3-c852b/P852B-092002 ? 2002 samsung electronics all rights reserved. no part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of samsung electronics. all semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. samsung electronics co., ltd. san #24 nongseo-ri, giheung-eup yongin-city, gyeonggi-do, korea c.p.o. box #37, suwon 440-900 tel: (82)-(31)-209-1934 fax: (82)-(31)-209-1899 home page: http://www.samsungsemi.com printed in the republic of korea
s3c852b/P852B microcontroller iii preface the s3c852b/P852B microcontroller user's manual is designed for application designers and programmers who are using the s3c852b/P852B microcontroller for application development. it is organized in two main parts: part i programming model part ii hardware descriptions part i contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. it has six chapters: chapter 1 product overview chapter 2 address spaces chapter 3 addressing modes chapter 4 control registers chapter 5 interrupt structure chapter 6 instruction set chapter 1, "product overview," is a high-level introduction to s3c851b/p851b with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. chapter 2, "address spaces," describes program and data memory spaces, the internal register file, and register addressing. chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations. chapter 3, "addressing modes," contains detailed descriptions of the addressing modes that are supported by the s3c8-series cpu. chapter 4, "control registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in a standardized format. you can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. chapter 5, "interrupt structure," describes the s3c852b/P852B interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in part ii. chapter 6, "instruction set," describes the features and conventions of the instruction set used for all ks88-series microcontrollers. several summary tables are presented for orientation and reference. detailed descriptions of each instruction are presented in a standard format. each instruction description includes one or more practical examples of how to use the instruction when writing an application program. a basic familiarity with the information in part i will help you to understand the hardware module descriptions in part ii. if you are not yet familiar with the s3c8-series microcontroller family and are reading this manual for the first time, we recommend that you first read chapters 1?3 carefully. then, briefly look over the detailed information in chapters 4, 5, and 6. later, you can reference the information in part i as necessary. part ii "hardware descriptions," has detailed information about specific hardware components of the s3c851b/p851b microcontroller. also included in part ii are electrical, mechanical, and otp. it has 13 chapters: chapter 7 clock circuits chapter 8 reset and power-down chapter 9 i/o ports chapter 10 basic timer and timer 0 chapter 11 timer 1 chapter 12 watch timer chapter 13 serial i/o port chapter 14 caller id block chapter 15 a/d converter chapter 16 extermal interface chapter 17 electrical data chapter 18 mechanical data chapter 19 s3P852B otp two order forms are included at the back of this manual to facilitate customer order for s3c852b/P852B microcontrollers: the mask rom order form, and the mask option selection form. you can photocopy these forms, fill them out, and then forward them to your local samsung sales representative.

s3c852b/P852B microcontroller v table of contents part i ? programming model chapter 1 product overview sam87rc product family ................................ ................................ ................................ ....................... 1-1 s3c852b microcontroller ................................ ................................ ................................ ......................... 1-1 otp ................................ ................................ ................................ ................................ ......................... 1-2 features ................................ ................................ ................................ ................................ .................. 1-3 block diagram ................................ ................................ ................................ ................................ ......... 1-4 pin assignments ................................ ................................ ................................ ................................ ...... 1-5 pin descriptions ................................ ................................ ................................ ................................ ....... 1-6 pin circuits ................................ ................................ ................................ ................................ .............. 1-10 chapter 2 address spaces overview ................................ ................................ ................................ ................................ ................. 2-1 program memory ( rom ) ................................ ................................ ................................ ......................... 2-2 register architecture ................................ ................................ ................................ ............................... 2-4 working registers ................................ ................................ ................................ ........................... 2-8 using the register pointers ................................ ................................ ................................ ............. 2-9 register addressing ................................ ................................ ................................ ................................ . 2-12 common working register area (c0h?cfh) ................................ ................................ .................. 2-14 4-bit working register addressing ................................ ................................ ................................ .. 2-16 8-bit working register addressing ................................ ................................ ................................ .. 2-18 system and user stacks ................................ ................................ ................................ .......................... 2-20 chapter 3 addressing modes overview ................................ ................................ ................................ ................................ ................. 3-1 register addressing mode (r) ................................ ................................ ................................ ......... 3-2 indirect register addressing mode (ir) ................................ ................................ ............................. 3-3 indexed addressing mode (x) ................................ ................................ ................................ .......... 3-7 direct address mode ( da) ................................ ................................ ................................ ............... 3-10 indirect address mode ( ia) ................................ ................................ ................................ .............. 3-12 relative address mode ( ra) ................................ ................................ ................................ ........... 3-13 immediate mode ( im) ................................ ................................ ................................ ...................... 3-14
vi s3c852b/P852B microcontroller table of contents (continued) chapter 4 control registers overview ................................ ................................ ................................ ................................ ................. 4-1 chapter 5 interrupt structure overview ................................ ................................ ................................ ................................ ................. 4-1 interrupt types ................................ ................................ ................................ ................................ 4-2 s 3c852b/P852B interrupt structure ................................ ................................ ................................ 4-3 interrupt vector addresses ................................ ................................ ................................ .............. 4-4 enable/disable interrupt instructions ( ei, di) ................................ ................................ ................... 4-6 system-level interrupt control registers ................................ ................................ ........................ 4-6 interrupt processing control points ................................ ................................ ................................ .. 4-7 system mode register ( sym ) ................................ ................................ ................................ .................. 4-8 interrupt mask register ( imr ) ................................ ................................ ................................ .......... 4-9 interrupt priority register ( ipr ) ................................ ................................ ................................ ........ 4-10 interrupt request register ( irq ) ................................ ................................ ................................ ..... 4-12 interrupt pending function types ................................ ................................ ................................ .... 4-13 interrupt source polling sequence ................................ ................................ ................................ .. 4-14 interrupt service routines ................................ ................................ ................................ ............... 4-14 generating interrupt vector addresses ................................ ................................ ............................ 4-15 nesting of vectored interrupts ................................ ................................ ................................ ......... 4-15 instruction pointer ( ip ) ................................ ................................ ................................ ..................... 4-15 fast interrupt processing ................................ ................................ ................................ ................. 4-16 chapter 6 instruction set overview ................................ ................................ ................................ ................................ ................. 6-1 data types ................................ ................................ ................................ ................................ ...... 6-1 register addressing ................................ ................................ ................................ ........................ 6-1 addressing modes ................................ ................................ ................................ ........................... 6-1 flags register ( flags ) ................................ ................................ ................................ .................. 6-6 flag descriptions ................................ ................................ ................................ ............................. 6-7 instruction set notation ................................ ................................ ................................ ................... 6-8 condition codes ................................ ................................ ................................ .............................. 6-12 instruction descriptions ................................ ................................ ................................ ................... 6-13
s3c852b/P852B microcontroller vii table of contents (continued) part ii hardware descriptions chapter 7 clock circuits overview ................................ ................................ ................................ ................................ ................. 7-1 system clock circuit ................................ ................................ ................................ ....................... 7-1 main oscillator circuits ................................ ................................ ................................ .................... 7-2 sub oscillator circuits ................................ ................................ ................................ ..................... 7-2 clock status during power-down modes ................................ ................................ ......................... 7-2 system clock control register (clkcon) ................................ ................................ ...................... 7-4 oscillator control register (osccon) ................................ ................................ ............................ 7-5 switching the cpu clock ................................ ................................ ................................ ................. 7-6 stop control register (stpcon) ................................ ................................ ................................ .... 7-7 phase locked loop (pll) ................................ ................................ ................................ ........................ 7-8 main clock generation ................................ ................................ ................................ .................... 7-8 doubling main clock frequency ................................ ................................ ................................ ...... 7-8 chapter 8 reset reset and power-down system reset ................................ ................................ ................................ ................................ .......... 8-1 overview ................................ ................................ ................................ ................................ ......... 8-1 normal mode reset operation ................................ ................................ ................................ ........ 8-2 rom-less mode reset operation ................................ ................................ ................................ .... 8-2 hardware reset values ................................ ................................ ................................ ................ 8-3 power-down modes ................................ ................................ ................................ ................................ . 8-6 stop mode ................................ ................................ ................................ ................................ ....... 8-6 idle mode ................................ ................................ ................................ ................................ ........ 8-7 chapter 9 i/o ports overview ................................ ................................ ................................ ................................ ................. 9-1 port data registers ................................ ................................ ................................ ......................... 9-3 port 0 ................................ ................................ ................................ ................................ .............. 9-4 port 1 ................................ ................................ ................................ ................................ .............. 9-7 port 2 ................................ ................................ ................................ ................................ .............. 9-10 port 3 ................................ ................................ ................................ ................................ .............. 9-11 port 4 ................................ ................................ ................................ ................................ .............. 9-13 port 5 ................................ ................................ ................................ ................................ .............. 9-14 port 6 ................................ ................................ ................................ ................................ .............. 9-15 port 7 ................................ ................................ ................................ ................................ .............. 9-16 port 8 ................................ ................................ ................................ ................................ .............. 9-17 port 9 ................................ ................................ ................................ ................................ .............. 9-18 port 10 ................................ ................................ ................................ ................................ ............ 9-19
viii s3c852b/P852B microcontroller table of contents (continued) chapter 10 basic timer & timer 0 module overview ................................ ................................ ................................ ................................ ..... 10-1 basic timer control register ( btcon ) ................................ ................................ ........................... 10-2 basic timer function description ................................ ................................ ................................ .... 10-3 timer 0 control register ( t0con ) ................................ ................................ ................................ .. 10-5 timer 0 function description ................................ ................................ ................................ ........... 10-7 chapter 11 timer 1 one 16-bit timer mode (timer 1) ................................ ................................ ................................ ............ 11-1 overview ................................ ................................ ................................ ................................ ......... 11-1 function description ................................ ................................ ................................ ........................ 11-1 block diagram ................................ ................................ ................................ ................................ ......... 11-3 two 8-bit timers mode (timer a and b) ................................ ................................ ................................ .. 11-4 overview ................................ ................................ ................................ ................................ ......... 11-4 function description ................................ ................................ ................................ ........................ 11-7 chapter 12 watch timer overview ................................ ................................ ................................ ................................ ................. 12-1 watch timer control register (wtcon) ................................ ................................ ......................... 12-2 watch timer circuit diagram ................................ ................................ ................................ .......... 12-3 chapter 13 serial i/o port overview ................................ ................................ ................................ ................................ ................. 13-1 programming procedure ................................ ................................ ................................ .................. 13-1 sio control register (siocon) ................................ ................................ ................................ ....... 13-2 sio prescaler register (siops) ................................ ................................ ................................ ....... 13-3 block diagram ................................ ................................ ................................ ................................ . 13-3 serial i/o timing diagrams ................................ ................................ ................................ ............. 13-4
s3c852b/P852B microcontroller ix table of contents (continued) chapter 14 caller id block overview ................................ ................................ ................................ ................................ ................. 14-1 function description of cid block ................................ ................................ ................................ ........... 14-3 analog input and preprocessor ................................ ................................ ................................ ........ 14-3 cas tone detection ................................ ................................ ................................ ........................ 14-5 fsk data reception ................................ ................................ ................................ ........................ 14-6 stutter dial tone( sdt ) detector ................................ ................................ ................................ ...... 14-8 ring or line reversal detector ................................ ................................ ................................ ........ 14-9 tone generator ................................ ................................ ................................ ............................... 14-11 melody generator ................................ ................................ ................................ ............................ 14-16 power-down mode of cid block ................................ ................................ ................................ ...... 14-18 interrupt of cid block ................................ ................................ ................................ ...................... 14-18 register maps of cid block ................................ ................................ ................................ ............. 14-19 chapter 15 a/d converter overview ................................ ................................ ................................ ................................ ................. 15-1 function description ................................ ................................ ................................ ................................ 15-1 a/d converter control register (adcon) ................................ ................................ ....................... 15-2 internal reference voltage levels ................................ ................................ ................................ ... 15-3 conversion timing ................................ ................................ ................................ .......................... 15-4 internal a/d conversion procedure ................................ ................................ ................................ . 15-5 chapter 16 external interface overview ................................ ................................ ................................ ................................ ................. 16-1 configuration options for external program memory ................................ ................................ ...... 16-3 external interface control registers ................................ ................................ ................................ 16-4 system mode register ( sym ) ................................ ................................ ................................ ......... 16-4 external memory timing register ( emt ) ................................ ................................ ......................... 16-5 port 3 alternative function select register ( p3afs ) ................................ ................................ ....... 16-6 port 4 control register ( p4con ) ................................ ................................ ................................ ..... 16-6 port 5 control register ( p5con ) ................................ ................................ ................................ ..... 16-6 port 6 control register ( p6con ) ................................ ................................ ................................ ..... 16-6 configuring separate external program and data memory areas ................................ ................... 16-8 external bus operations ................................ ................................ ................................ .................. 16-9 sam8 instruction execution timing diagrams ................................ ................................ ................. 16-15
x s3c852b/P852B microcontroller table of contents (concluded ) chapter 17 ele ctrical data overview ................................ ................................ ................................ ................................ ................. 17-1 chapter 18 mechanical data overview ................................ ................................ ................................ ................................ ................. 18-1 chapter 19 s3P852B otp overview ................................ ................................ ................................ ................................ ................. 19-1 operating mode characteristics ................................ ................................ ................................ ....... 19-3
s3c852b/P852B microcontroller xi list of figures figure title page number number 1-1 block diagram ................................ ................................ ................................ ........ 1-4 1-2 pin assignment (100-pin qfp package) ................................ ................................ 1-5 1-3 pin circuit type 1 ................................ ................................ ................................ ... 1-10 1-4 pin circuit type 2 (reset) ................................ ................................ .................... 1-10 1-5 pin circuit type 3 (port 0) ................................ ................................ ...................... 1-10 1-6 pin circuit type 4 (port 1.0-port 1.3) ................................ ................................ ...... 1-11 1-7 pin circuit type 5 (port 3) ................................ ................................ ...................... 1-12 1-8 pin circuit type 6 (port 4, 5, 6) ................................ ................................ .............. 1-12 2-1 program memory address space ................................ ................................ ........... 2-2 2-2 internal register file organization ................................ ................................ ......... 2-4 2-3 register page pointer (pp) ................................ ................................ .................... 2-6 2-4 map of set 1, set 2, and prime register spaces ................................ .................... 2-7 2-5 8-byte working register areas (slices) ................................ ................................ .. 2-8 2-6 contiguous 16-byte working register block ................................ .......................... 2-10 2-7 non-contiguous 16-byte working register block ................................ ................... 2-10 2-8 16-bit register pairs ................................ ................................ .............................. 2-12 2-9 register file addressing ................................ ................................ ......................... 2-13 2-10 common working register area ................................ ................................ ............ 2-14 2-11 4-bit working register addressing ................................ ................................ ......... 2-17 2-13 4-bit working register addressing e xample ................................ .......................... 2-17 2-13 8-bit working register addressing ................................ ................................ ......... 2-18 2-14 8-bit working register addressing example ................................ .......................... 2-19 2-15 stack operations ................................ ................................ ................................ .... 2-20 3-1 register addressing ................................ ................................ ............................... 3-2 3-2 working register addressing ................................ ................................ ................. 3-2 3-3 indirect register addressing to register file ................................ .......................... 3-3 3-4 indirect register addressing to program memory ................................ ................... 3-4 3-5 indirect working register addressing to register file ................................ ............ 3-5 3-6 indirect working register addressing to program or data memory ........................ 3-6 3-7 indexed addressing to register file ................................ ................................ ....... 3-7 3-8 indexed addressing to program or data memory with short offset ........................ 3-8 3-9 indexed addressing to program or data memory ................................ ................... 3-9 3-10 direct addressing for load instructions ................................ ................................ .. 3-10 3-11 direct addressing for call and jump instructions ................................ .................... 3-11 3-12 indirect addressing ................................ ................................ ................................ . 3-12 3-13 relative addressing ................................ ................................ ............................... 3-13 3-14 immediate addressing ................................ ................................ ............................ 3-14
xii s3c852b/P852B microcontroller list of figures (continued) figure title page number number 4-1 register description format ................................ ................................ ................... 4-4 5-1 sam8-series interrupt types ................................ ................................ .................. 5-2 5-2 s3c852b interrupt structure ................................ ................................ ................... 5-3 5-3 vector address area in p rogram memory (rom) ................................ ................... 5-4 5-4 interrupt function diagram ................................ ................................ ..................... 5-7 5-5 system mode register (sym) ................................ ................................ ................ 5-8 5-6 interrupt mask register (imr) ................................ ................................ ................. 5-9 5-7 interrupt request priority groups ................................ ................................ ........... 5-10 5-8 interrupt priority register (ipr) ................................ ................................ ............... 5-11 5-9 interrupt request register (irq) ................................ ................................ ............ 5-12 6-1 system flags register (flags) ................................ ................................ ............. 6-6 7-1 crystal oscillator ................................ ................................ ................................ .... 7-2 7-2 crystal oscillator ................................ ................................ ................................ .... 7-2 7-3 system clock circuit diagram ................................ ................................ ................ 7-3 7-4 system clock control register (clkcon) ................................ ............................. 7-4 7-5 oscillator control register (osccon) ................................ ................................ ... 7-5 7-6 stop control regis ter (stpcon) ................................ ................................ ......... 7-7 9-1 s3c852b i/o port data register format ................................ ................................ 9-3 9-2 port 0 control register (p0conh) ................................ ................................ ......... 9-5 9-3 port 0 control register (p0conl) ................................ ................................ .......... 9-5 9-4 port 0 interrupt enable register (p0int) ................................ ................................ 9-6 9-5 port 0 interrupt pending register (p0pnd) ................................ ............................. 9-6 9-6 port 0 interrupt state register (p0sta) ................................ ................................ .. 9-6 9-7 port 1 high-byte control register (p1conh) ................................ ......................... 9-8 9-8 port 1 low-byte control register (p1conl) ................................ .......................... 9-8 9-9 port 1 alternative function select register (p1afs) ................................ .............. 9-9 9-10 port 2 control register (p2con) ................................ ................................ ............ 9-10 9-11 port 3 control register (p3con) ................................ ................................ ............ 9-12 9-12 port 3 alternative function select register (p3afs) ................................ .............. 9-12 9-13 port 4 control register (p4con) ................................ ................................ ............ 9-13 9-14 port 5 control register (p5con) ................................ ................................ ............ 9-14 9-15 port 6 control register (p6con) ................................ ................................ ............ 9-15 9-16 port 7 high-byte control register (p7conh) ................................ ......................... 9-16 9-17 port 7 low-byte control register (p7conl) ................................ .......................... 9-16 9-18 port 8 high-byte control register (p8conh) ................................ ......................... 9-17 9-19 port 8 low-byte control register (p8conl) ................................ .......................... 9-17 9-20 port 9 high-byte control register (p9conh) ................................ ......................... 9-18 9-21 port 9 lo w-byte control register (p9conl) ................................ .......................... 9-18 9-22 port 10 high-byte control register (p10conh) ................................ ..................... 9-19 9-23 port 10 low-byte control register (p10conl) ................................ ....................... 9-19
s3c852b/P852B microcontroller xiii list of figures (continued) page title page number number 10-1 basic timer control register (btcon) ................................ ................................ .. 10-2 10-2 basic timer block diagram ................................ ................................ .................... 10-4 10-3 timer 0 control register (t0con) ................................ ................................ ......... 10-6 10-4 simplified timer 0 function diagram: interval timer mode ................................ .... 10-7 10-5 simplified timer 0 function diagram: pwm mode ................................ ................. 10-8 10-6 simplified timer 0 function diag ram: capture mode ................................ ............. 10-9 10-7 timer 0 block diagram ................................ ................................ ........................... 10-10 11-1 timer 1 control register (tacon) ................................ ................................ ......... 11-2 11-2 timer 1 functional block diagram ................................ ................................ ......... 11-3 11-3 timer a control register (tacon) ................................ ................................ ........ 11-5 11-4 timer b control register (tbcon) ................................ ................................ ........ 11-6 11-5 timer a and b function block diagram ................................ ................................ .. 11-8 11-6 timer b pwm function block diagram ................................ ................................ .. 11-9 12-1 watch timer control register (wtcon) ................................ ............................... 12-2 12-2 watch timer circuit diagram ................................ ................................ ................. 12-3 13-1 serial i/o module control registers (siocon) ................................ ...................... 13-2 13-2 sio prescaler register (siops) ................................ ................................ ............. 13-3 13-3 sio functional block diagram ................................ ................................ ............... 13-3 13-4 sio timing in transmit/receive mode (tx at falling edge, siocon.4=0) .............. 13-4 13-5 sio timing in transmit/receive mode (tx at rising edge, siocon.4=1) ............... 13-4 13-6 sio timing in receive-only mode (rising edge start) ................................ ............ 13-5 14-1 cid part functional block diagram ................................ ................................ ........ 14-2 14-2 differential i nput b uffer of the s3c852b ................................ ................................ . 14-3 14-3 single e nded b uffer of the s3c852b ................................ ................................ ...... 14-4 14-4 casdetect, casint and int r elated to the cas tone ................................ ............ 14-5 14-5 sequence to r eceive an fsk d ata b yte ................................ ................................ 14-6 14-6 interrupt behavior of the fsk receiver with bomdc = 1 ................................ ......... 14-7 14-7 interrupt behavior of the fsk receiver with bomdc = 0 ................................ ......... 14-7 14-8 sdt d etector o peration ................................ ................................ ......................... 14-8 14-9 external c omponent to g enerate lrin ................................ ................................ ... 14-9 14-10 behavior of s ignals on a l ine r eversal ................................ ................................ .. 14-10 14-11 behavior of s ignals d uring r ing ................................ ................................ ............. 14-10 14-12 tone g enerator b lock ................................ ................................ ............................ 14-11 14-13 block d iagram of nco ................................ ................................ ........................... 14-12 14-14 block d iagram of m elody g enerator ................................ ................................ ....... 14-17
xiv s3c852b/P852B microcontroller list of figures (continued) page title page number number 15-1 a/d c onverter control register (adcon) ................................ .............................. 15-2 15-2 a/d converter data register (addatah/addatal) ................................ ............. 15-2 15-3 a/d converter circuit diagram ................................ ................................ ............... 15-3 15-4 a/d converter timing diagram ................................ ................................ .............. 15-4 15-5 recommended a/d converter circuit for highest absolute accuracy ..................... 15-5 16-1 s3c852b external memory interface function diagram ................................ ......... 16-2 16-2 internal and external program memory options ................................ ..................... 16-3 16-3 system mode register (sym) ................................ ................................ ................ 16-4 16-4 external memory timing control register (emt) ................................ ................... 16-5 16-5 external bus write cycle timing diagram (add ress, and data separated ) ............ 16-10 16-6 external bus read cycle timing diagram ................................ .............................. 16-11 16-7 external interface function diagram (with sram and eprom or eeprom) ......... 16-13 16-8 external interface function diagram (external rom only) ................................ ..... 16-14 16-9 external bus timing diagram for 1-byte fetch instructions ................................ .... 16-15 16-10 external bus timing diagram for 2-byte fetch instructions ................................ .... 16-15 16-11 external bus timing diagram for 3-byte fetch instructions ................................ .... 16-16 16-12 external bus timing diagram for 4-byte fetch instructions ................................ .... 16- 16 17-1 stop mode release timing when initiated by an external interrupt ....................... 17-5 17-2 stop mode release timing when initiated by a reset ................................ ......... 17-6 17-3 input timing for external interrupts (p0.0?p0.7) ................................ ..................... 17-7 17-4 input timing for reset ................................ ................................ ......................... 17-7 17-5 clock timing measurement at x in ................................ ................................ .......... 17-9 17-6 clock timing measurement at xt in ................................ ................................ ........ 17-9 17-7 serial data transfer timing ................................ ................................ .................... 17-11 17-8 waveform for cas timing characteristics ................................ ............................. 17-14 18-1 100-pin qfp package mechanical data ................................ ................................ . 18-2 19-1 s3P852B pin assignments (100-pin qfp packa ge) ................................ ............... 19-2
s3c852b/P852B microcontroller xv list of tables table title page number number 1-1 pin descriptions ................................ ................................ ................................ ..... 1-6 2-1 s3c852b register type summary ................................ ................................ ......... 2-4 4-1 set 1, bank 0 registers ................................ ................................ .......................... 4-2 4-2 set 1, bank 1 registers ................................ ................................ .......................... 4-3 5-1 s3c852b/P852B interrupt vectors ................................ ................................ ......... 5-5 5-2 interrupt control register overview ................................ ................................ ....... 5-6 6-1 instruction group summary ................................ ................................ .................... 6-2 6-2 flag notation conventions ................................ ................................ ..................... 6-8 6-3 instruction set symbols ................................ ................................ .......................... 6-8 6-4 instruction notation conventions ................................ ................................ ............ 6-9 6-5 opcode quick reference ................................ ................................ ....................... 6-10 6-6 condition codes ................................ ................................ ................................ ..... 6-12 8-1 s3c851b/P852B set 1 register and values after reset (masked rom mode) ................................ ................................ ............................. 8-3 8-2 s3c851b/P852B set 1, bank 0 register and values after reset (masked rom mode) ................................ ................................ ............................. 8-4 8-3 s3c851b/P852B set 1, bank 1 register values after reset (masked rom mode) ................................ ................................ ............................. 8-5 9-1 s3c851b port configuration overview ................................ ................................ ... 9-2 9-2 port data register summary ................................ ................................ .................. 9-3 14-1 cas detector parameters ................................ ................................ ....................... 14-5 14-2 fsk receiver p arameters ................................ ................................ ...................... 14-6 14-3 stutter dial t one p arameters ................................ ................................ .................. 14-8 14-4 dtmf frequencies code and phase input data ................................ ..................... 14-14 14-5 dual tone frequency of cas and phase input da ta ................................ .............. 14-14 14-6 fsk parameters ................................ ................................ ................................ ..... 14-15 14-7 the frequencies and mref1 register values for 3 octave musical scale ............ 14-16 14-8 interrupt sources of the cid block ................................ ................................ ......... 14-18 14-9 register overview ................................ ................................ ................................ .. 14-19
xvi s3c852b/P852B microcontroller list of tables (continued) table title page number number 16-1 control register overview for the external interface ................................ .............. 16-6 16-2 external interface control register values after a reset (normal mode) ............. 16-7 16-3 external interface control register values after a reset (rom-less mode) ......... 16-7 16-4 s3c852b external memory interface signal descriptions ................................ ....... 16-12 17-1 absolute maximum ratings ................................ ................................ .................... 17-2 17-2 d.c. electrical characteristics ................................ ................................ ................ 17-3 17-3 data retention supply voltage in stop mode ................................ ......................... 17-5 17-4 input/output capacitance ................................ ................................ ....................... 17-7 17-5 a.c. electrical characteristics ................................ ................................ ................ 17-7 17-6 main oscillation characteristics ................................ ................................ .............. 17-8 17-7 sub oscillation characteristics ................................ ................................ ............... 17-8 17-8 main oscillation stabilization time ................................ ................................ ......... 17-9 17-9 sub oscillation stabilization time ................................ ................................ .......... 17-9 17-10 phase locked loop characteristics ................................ ................................ ........ 17-10 17-11 serial i/o timing cha racteristics ................................ ................................ ............ 17-11 17-12 a/d converter electrical characteristics ................................ ................................ . 17-12 17-13 electrical c haracteristics of cid block ( r eceiver & d etectors) ............................... 17-13 17-14 cas t iming c haracteristics ................................ ................................ .................... 17-14 17-15 electrical c haracteristics of cid block ( t one g enerator) ................................ ........ 17-14 17-16 sdt t iming c haracteristics ................................ ................................ .................... 17-15 19-1 descriptions of pins used to read/write the eprom ................................ ............. 19-3 19-2 comparison of s3P852B and s3c852b features ................................ ................... 19-3
s3c852b/P852B microcontroller xvii list of programming tips description page number chapter 2: address spaces setting the register pointers ................................ ................................ ................................ ............... 2-9 addressing the common working register area ................................ ................................ ................. 2-15 standard stack operations using push and pop ................................ ................................ .............. 2-21 chapter 5: interrupt structure setting up the s3c852b interrupt control structure ................................ ................................ ............ 5-18 chapter 7: clock circuits switching the cpu clock ................................ ................................ ................................ ...................... 7-6 chapter 8: reset reset and power-down sample s3c852b initialization routine ................................ ................................ ............................... 8-8 chapter 10: basic timer and timer 0 configuring the basic timer ................................ ................................ ................................ .............. 10-11 programming timer 0 ................................ ................................ ................................ .......................... 10-12 chapter 13: serial i/o port use internal clock to transfer and receive serial data ................................ ................................ ...... 13-5 chapter 15: a/d converter configuring a/d converter ................................ ................................ ................................ .................. 15-6

s3c852b/P852B microcontroller xix list of register descriptions register full register name page identifier number adcon a/d converter control register ................................ ................................ .............. 4-5 btcon basic timer control register ................................ ................................ .................. 4-6 clkcon system clock control register ................................ ................................ ............... 4-7 clkmod clock output mode register ................................ ................................ ................... 4-8 emt external memory timing register ................................ ................................ .......... 4-9 flags system flags register ................................ ................................ ........................... 4-10 imr interrupt mask register ................................ ................................ .......................... 4-11 intpnd interrupt pending register ................................ ................................ ...................... 4-12 iph instruction pointer (high byte) ................................ ................................ ................ 4-13 ipl instruction po inter (low byte) ................................ ................................ ................. 4-13 ipr interrupt priority register ................................ ................................ ........................ 4-14 irq interrupt request register ................................ ................................ ...................... 4-15 osccon oscillator control register ................................ ................................ ...................... 4-16 p0conh port 0 control register (high byte) ................................ ................................ ......... 4-17 p0conl port 0 control register(low byte) ................................ ................................ ........... 4-18 p0int port 0 interrupt enable register ................................ ................................ ............. 4-19 p0pnd port 0 interrupt pending register ................................ ................................ ........... 4-20 p0sta port 0 interrupt state register ................................ ................................ ................ 4-21 p1afs port 1 function select register ................................ ................................ .............. 4-22 p1conh port 1 control register(high byte) ................................ ................................ .......... 4-23 p1conl port 1 control register(low byte) ................................ ................................ ........... 4-24 p2con port 2 control register ................................ ................................ ........................... 4-25 p3afs port 3 function select register ................................ ................................ .............. 4-26 p3con port 3 control register ................................ ................................ ........................... 4-27 p4con port 4 control register ................................ ................................ ........................... 4-28 p5con port 5 control register ................................ ................................ ........................... 4-29 p6con port 4 control register ................................ ................................ ........................... 4-30 p7conh port 7 control register(high byte) ................................ ................................ .......... 4-31 p7conl port 7 control register(low byte) ................................ ................................ ........... 4-32 p8conh port 8 control register(high byte) ................................ ................................ .......... 4-33 p8conl port 8 control register(low byte) ................................ ................................ ........... 4-34 p9conh port 9 control register(high byte) ................................ ................................ .......... 4-35 p9conl port 9 control register(low byte) ................................ ................................ ........... 4-36 p10conh port 10 control regi ster(high byte) ................................ ................................ ........ 4-37 p10conl port 10 control register(low byte) ................................ ................................ ......... 4-38
xx s3c852b/P852B microcontroller list of register descriptions (continued) register full register name page identifier number pp register page pointer ................................ ................................ ............................. 4-39 rp0 register pointer 0 ................................ ................................ ................................ ... 4-40 rp1 register pointer 1 ................................ ................................ ................................ ... 4-40 siocon sio control register ................................ ................................ .............................. 4-41 siops sio prescaler register ................................ ................................ ........................... 4-42 sph stack pointer (high byte) ................................ ................................ ....................... 4-43 spl stack pointer (low byte) ................................ ................................ ........................ 4-43 stpcon stop control register ................................ ................................ ............................. 4-44 sym system mode register ................................ ................................ ........................... 4-45 t0con timer a control register ................................ ................................ ........................ 4-46 tacon timer a control reg ister ................................ ................................ ........................ 4-47 tbcon timer b control register ................................ ................................ ........................ 4-48 wtcon watch timer control register ................................ ................................ ................ 4-49
s3c852b/P852B microcontroller xxi list of instruction descriptions instruction full register name page mnemonic number adc add with carry ................................ ................................ ................................ ........ 6-14 add add ................................ ................................ ................................ ........................ 6-15 and logical and ................................ ................................ ................................ ........... 6-16 band bit and ................................ ................................ ................................ .................. 6-17 bcp bit compare ................................ ................................ ................................ ........... 6-18 bitc bit complement ................................ ................................ ................................ ..... 6-19 bitr bit reset ................................ ................................ ................................ ................ 6-20 bits bit set ................................ ................................ ................................ .................... 6-21 bor bit or ................................ ................................ ................................ .................... 6-22 btjrf bit test, jump relative on false ................................ ................................ ............ 6-23 btjrt bit test, jump relative on true ................................ ................................ ............. 6-24 bxor bit xor ................................ ................................ ................................ .................. 6-25 call call procedure ................................ ................................ ................................ ....... 6-26 ccf complement carry flag ................................ ................................ ......................... 6-27 clr clear ................................ ................................ ................................ ...................... 6-28 com complement ................................ ................................ ................................ ........... 6-29 cp compare ................................ ................................ ................................ ................ 6-30 cpije compare, increment, and jump on equal ................................ .............................. 6-31 cpijne compare, increment, and jump on non-equal ................................ ....................... 6-32 da decimal adjust ................................ ................................ ................................ ....... 6-33 dec decrement ................................ ................................ ................................ ............. 6-35 decw decrement word ................................ ................................ ................................ .... 6-36 di disable interrupts ................................ ................................ ................................ ... 6-37 div divide (unsigned) ................................ ................................ ................................ ... 6-38 djnz decrement and jump if non-zero ................................ ................................ .......... 6-39 ei enable interrupts ................................ ................................ ................................ .... 6-40 enter enter ................................ ................................ ................................ ...................... 6-41 exit exit ................................ ................................ ................................ ........................ 6-42 idle idle operation ................................ ................................ ................................ ........ 6-43 inc increment ................................ ................................ ................................ ............... 6-44 incw increment word ................................ ................................ ................................ ..... 6-45 iret interrupt return ................................ ................................ ................................ ...... 6-46 jp jump ................................ ................................ ................................ ...................... 6-47 jr jump relative ................................ ................................ ................................ ........ 6-48 ld load ................................ ................................ ................................ ....................... 6-49 ldb load bit ................................ ................................ ................................ .................. 6-51
xxii s3c852b/P852B microcontroller list of instruction descriptions (continued) instruction full register name page mnemonic number ldc/lde load memory ................................ ................................ ................................ ......... 6-52 ldcd/lded load memory and decrement ................................ ................................ ................ 6-54 ldci/ldei load memory and increment ................................ ................................ .................. 6-55 ldcpd/ldepd load memory with pre-decrement ................................ ................................ ......... 6-56 ldcpi/ldepi load memory with pre-increment ................................ ................................ ........... 6-57 ldw load word ................................ ................................ ................................ ............. 6-58 mult multiply (unsigned) ................................ ................................ ................................ . 6-59 next next ................................ ................................ ................................ ....................... 6-60 nop no operation ................................ ................................ ................................ .......... 6-61 or logical or ................................ ................................ ................................ ............. 6-62 pop pop from stack ................................ ................................ ................................ ....... 6-63 popud pop user stack ( decrementing) ................................ ................................ ............. 6-64 popui pop user stack (incrementing) ................................ ................................ ............... 6-65 push push to stack ................................ ................................ ................................ ......... 6-66 pushud push user stack ( decrementing) ................................ ................................ ............ 6-67 pushui push user stack (incrementing) ................................ ................................ ............. 6-68 rcf reset carry flag ................................ ................................ ................................ .... 6-69 ret return ................................ ................................ ................................ .................... 6-70 rl rotate left ................................ ................................ ................................ ............. 6-71 rlc rotate left through carry ................................ ................................ ....................... 6-72 rr rotate right ................................ ................................ ................................ ........... 6-73 rrc rotate right through carry ................................ ................................ ..................... 6-74 sb0 select bank 0 ................................ ................................ ................................ ......... 6-75 sb1 select bank 1 ................................ ................................ ................................ ......... 6-76 sbc subtract with carry ................................ ................................ ................................ . 6-77 scf set carry flag ................................ ................................ ................................ ........ 6-78 sra shift right arithmetic ................................ ................................ .............................. 6-79 srp/srp0/srp1 set register pointer ................................ ................................ ............................... 6-80 stop stop operation ................................ ................................ ................................ ....... 6-81 sub subtract ................................ ................................ ................................ .................. 6-82 swap swap nibbles ................................ ................................ ................................ ......... 6-83 tcm test complement under mask ................................ ................................ ................ 6-84 tm test under mask ................................ ................................ ................................ ..... 6-85 wfi wait for interrupt ................................ ................................ ................................ .... 6-86 xor logical exclusive or ................................ ................................ ............................. 6-87
s3c852b/P852B (p reliminary s pec ) product overview 1- 1 1 product overview sam87rc product family samsung's new sam87rc family of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. timer/counters with selectable operating modes are included to support real-time operations. many sam87rc microcontrollers have an external interface that provides access to external memory and other peripheral devices. the sophisticated interrupt structure recognizes up to eight interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum six cpu clocks) can be assigned to specific interrupt levels. s3c852b microcontroller the s3c852b is a low power cmos 8-bit micro controller, which has a micro control unit (mcu), caller id on call waiting (cidcw) receiver, tone generator, etc. the s3c852b single-chip microcontroller is fabricated using a highly advanced cmos process. its design is based on the powerful sam87rc cpu core. stop and idle power-down modes were implemented to reduce power consumption. the s3c852b is used for receiving physical layer signals like bellcore's cpe alerting signal (cas) and similar evolving systems and also meets the requirements of emerging caller id on call waiting (cidcw) services. in addition, two different signal inputs are available to support tip/ring and hybrid connectivity. the device also includes a 1200 baud bell 202/v.23 compatible fsk data demodulator, a ring or line reversal detector, a stutter dial tone detector and a tone generator. tone generator is capable of generating fsk signal and dual tone signals such as cas, dtmf to support various applications such as short messaging service (sms). the size of the internal register file is logically expanded, increasing the addressable on-chip register space to 1808 bytes. a flexible yet sophisticated external interface is used to access up to 64-kbytes of program and data memory. the s3c852b is a versatile microcontroller that is ideal for use in a wide range of following applications. bellcore cid and cidcw systems cid and cidcw feature phones and adjunct boxes voice-mail and short messaging service (sms) equipment using the s3c852b modular design approach, the following peripherals were integrated with the sam87rc cpu core: large number of programmable i/o ports (total 80 pins) one synchronous sio module one 8-bit timer/counter (including interval mode, capture mode, pwm mode) one 16-bit timer/counter (including one 16-bit timer/counter mode and two 8-bit timer/counter mode) a/d converter with 4 selectable input pins
product overview s3 c852b/P852B (p reliminary s pec ) 1- 2 otp the s3c852b microcontroller is also available in otp(one time programmable) version, s3P852B. the s3P852B microcontroller has an on-chip 64k-byte one-time-programmable eprom instead of masked rom. the s3P852B is comparable to s3c852b, both in function and in pin configuration.
s3c852b/P852B (p reliminary s pec ) product overview 1- 3 features cpu sam87rc cpu core memory 1808-byte of internal register file 64-kbyte internal program memory area external interface 64-kbyte external data memory area 64-kbyte external program memory (romless) instruction set 78 instructions idle and stop instructions instruction execution time 558ns at 7.15909mhz fx (minimum) 122us at 32.768khz (sub clock) interrupts seven interrupt levels eight external interrupt pins timer / counters one 8-bit basic timer for watchdog function one 8-bit timer/counter (timer 0) with three operating mode; interval, capture, pwm one 16-bit timer/counter ? one 16-bit timer/counter mode ? two 8-bit timer/counters a/b mode ? timer/counter b including pwm mode (6, 7, 8-bit pwm with 1-channel output : push-pull type) watch timer interval time:3.91ms, 0.25s, 0.5s, 1s at 32.768 khz four frequency outputs to buz pin 8-bit serial i/o 8-bit transmit/receive mode 8-bit receive mode selectable baud rate or external clock source g eneral i/o 80-bit i/o pins analog to digital converter four analog input pins 10-bit conversion resolution internal av ref , av ss only c aller id r eceiver fsk demodulator with sensitivity -45dbm (in 600 w ) conforms to bell 202 and ccitt v.23 standards receive sensitivity of ?38dbm (in 600 w ) for cas stutter dial tone detector with sensitivity ?38dbm (in 600 w ) ring or line reversal detector on-hook and off-hook applications according to bellcore gr-30-core and sr-tsv-002476 compatible with etsi standards ets 300 659-1 and ets 300 659-2 tone generators dual tone generator with gain controller fsk tone sequence generator with 1200bps 3 octave melody generator power-down modes main idle mode (only cpu clock stops) sub idle mode (only cpu clock stops) stop mode (main or sub oscillation stops) oscillation sources crystal for main clock (fx) crystal for sub clock (fxt: 32.768khz) pll for 7.159090mhz pll for generating fx (3.579545mhz) from fxt operating temperature range 0 c to + 70 c operating voltage range 2.7 v to 5.5 v
product overview s3 c852b/P852B (p reliminary s pec ) 1- 4 package type 100-pin qfp package block diagram p0.6/int6 p0.5/int5 p0.3/int3 p0.1/int1 test p0.2/int2 p0.4/int4 basic timer 64-kbyte rom 14-bit a/d converter pulse density modulator xin x out xtin xtout p0.1/buz p0.2/t0ck p0.3/t0/t0cap p0.4/t1ck p0.5/ta p0.7/int7 p4.0-p4.7 p1.0-p1.7 inp inn out vref generator vref ins toneo rstb ea/vpp lrin i/o port and interrupt control p0.6/tb p5.0-p5.7 p6.0-p6.7 mld adc2/p1.2 adc1/p1.1 adc0/p1.0 adc3/p1.3 p1.4/si p1.5/so p1.6/ sck p2.2 p2.1 p2.0 p2.3 mcu block port7/port8/port9/ port10 p7.0-p7.7, p8.0-p8.7, p9.0-p9.7 p10.0-p10.7, p0.0/int0 p3.0-p3.3 pll melody generator fsk/dual tone generator cas/sdt detector fsk receiver lr/ring sam8 cpu lr/ring 2048-byte register file main osc sub osc watch timer timer 0 timer 1 serial i/o a/d converter port 0 port 1 port 2 port 4 port 5 port 6 port 3 pllc cksel figure 1-1. block diagram
s3c852b/P852B (p reliminary s pec ) product overview 1- 5 pin assignments p5.7/a7 p5.6/a6 p5.5/a5 p5.4/a4 p5.3/a3 p5.2/a2 p5.1/a1 p5.0/a0 p4.7/d7 p4.6/d6 p4.5/d5 p4.4/d4 p4.3/d3 p4.2/d2 p4.1/d1 p4.0/d0 p3.3/ wr p3.2/ rd p3.1/ dm p3.0/ pm p7.7 p7.6 p7.5 p7.4 p7.3 p0.7/int7 p0.6/int6/tb p0.5/int5/ta p0.4/int4/t1ck p0.3/int3/t0/t0cap p2.0 p2.1 p2.2(sdat) p2.3(sclk) v dd v ss x out x in ea xt in xt out reset p0.0/int0 p0.1/int1/buz p0.2/int2/t0ck p9.7 p9.6 p9.5 p9.4 p9.3 s3c852b/P852B 100-qfp-1420c 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 p8.7 p8.6 p8.5 p8.4 p8.3 p8.2 p8.1 p8.0 pllc cksel p7.2 p7.1 p7.0 vdda inp inn out ins v ref toneo vssa lr in mldo p10.7 p10.6 p10.5 p10.4 p10.3 p10.2 p10.1 p10.0 p6.7/a15 p6.6/a14 p6.5/a13 p6.4/a12 p6.3/a11 p6.2/a10 p6.1/a9 p6.0/a8 p1.7/ssd/sd3 p1.6/ sck /sd2 p1.5/so/sd1 p1.4/si/sd0 p1.3/adc3 p1.2/adc2 p1.1/adc1 p1.0/adc0 p9.0 p9.1 p9.2 figure 1-2. pin assignment (100-pin qfp package)
product overview s3 c852b/P852B (p reliminary s pec ) 1- 6 pin descriptions table 1-1. pin descriptions pin names pin type pin no. pin description vdda supply 67 positive supply voltage for analog operation inp analog i nput 66 input op-amp positive signal input for cas, fsk and sdt inn analog i nput 65 input op-amp negative signal input for cas, fsk and sdt out analog output 64 input op-amp output signal for cas, fsk and sdt ins analog i nput 63 input op-amp single ended input signal for cas v ref analog output 62 reference voltage for input signal toneo analog o utput 61 fsk and dual tone signal output vssa supply 60 negative supply pin for analog operation (ground) lr in schmitt i nput 59 input for line reversal or ring detection test input 71 test pin, must be connected to ground v dd supply 15 positive supply voltage v ss supply 16 negative supply voltage (ground) x out , x in ? 17,18 3.579545 mhz crystal input/output ea/v pp ? 19 must be connected to ground (in case of otp writing, it should be connected to v pp ) xt in , xt out ? 20,21 crystal oscillator pins for sub clock (32.768khz) rstb input 22 resets the s3c852b to known state mldo output 58 melody output cksel ? 71 pll output/x in selection pllc analog input 72 pll capacitor p0.0/int0 p0.1/int1/buz p0.2/int2/t0ck p0.3/int3/t0cap/t0 p0.4/int4/t1ck p0.5/int5/ta p0.6/int6/tb p0.7/int7 i/o 23 24 25 10 9 8 7 6 i/o port with bit-programmable pins; schmitt trigger input or push-pull output and software assignable pull-up; alternative usage: p0.1-p0.7 : external interrupt input (p0.0 used for cid interrupt handling); p0.1 : buzzer signal output pin; p0.2 : timer0 clock input pin; p0.3 : timer0 capture input or interval/pwm output pin; p0.4 : tomer1 external clock input pin; p0.5 & p0.6 : timer a & timer b clock output pin;
s3c852b/P852B (p reliminary s pec ) product overview 1- 7 table 1-1. pin descriptions (continued) pin names pin type pin no. pin description p1.0/adc0 p1.1/adc1 p1.2/adc2 p1.3/adc3 p1.4/si /sd0 p1.5/so/ sd1 p1.6/ sck /sd2 p1.7/ssd/sd3 i/o 34 35 36 37 38 39 40 41 i/o port with bit-programmable pins; schmitt trigger input or push-pull, open-drain output and software assignable pull-up; alternative usage: p1.0-p1.3 : four channel analog inputs; p1.4 : serial data input p1.5 : serial data output p1.6 : serial i/o interface clock signal p2.0 p2.1 p2.2/sdat p2.3/sclk i/o 11 12 13 14 i/o port with bit-programmable pins; schmitt trigger input or push-pull, open-drain output and software assignable pull-up; alternative usage: p2.2 : serial data pin for otp writing p2.3 : serial clock pin for otp writing p3.0 p3.1 p3.2 p3.3 i/o 100 99 98 97 i/o port with bit-programmable pins; schmitt trigger input or push-pull, open-drain output and software assignable pull-up; p3.0-p3.4 are configurable for external interface signals p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 i/o 96 95 94 93 92 91 90 89 i/o port with bit-programmable pins; schmitt trigger input or push-pull, open-drain output and software assignable pull-up; alternative usage: p4 is configurable for external interface data lines d0-d7 p5.0 p5.1 p5.2 p5.3 p5.4 p5.5 p5.6 p5.7 i/o 88 87 86 85 84 83 82 81 i/o port with bit-programmable pins; schmitt trigger input or push-pull, open-drain output and software assignable pull-up; alternative usage: p5 is configurable for external interface address lines a0-a7
product overview s3 c852b/P852B (p reliminary s pec ) 1- 8 table 1-1. pin descriptions (continued) pin names pin type pin no. pin description p6.0 p6.1 p6.2 p6.3 p6.4 p6.5 p6.6 p6.7 i/o 42 43 44 45 46 47 48 49 i/o port with bit-programmable pins; schmitt trigger input or push-pull, open-drain output and software assignable pull-up; alternative usage: p6 is configurable for external interface address lines a8-a15 p7.7 p7.6 p7.5 p7.4 p7.3 p7.2 p7.1 p7.0 i/o 5 4 3 2 1 70 69 68 i/o port with bit-programmable pins; schmitt trigger input or push-pull, open-drain output and software assignable pull-up; p8.0 p8.1 p8.2 p8.3 p8.4 p8.5 p8.6 p8.7 i/o 73 74 75 76 77 78 79 80 i/o port with bit-programmable pins; schmitt trigger input or push-pull, open-drain output and software assignable pull-up; p9.0 p9.1 p9.2 p9.3 p9.4 p9.5 p9.6 p9.7 i/o 33 32 31 30 29 28 27 26 i/o port with bit-programmable pins; schmitt trigger input or push-pull, open-drain output and software assignable pull-up;
s3c852b/P852B (p reliminary s pec ) product overview 1- 9 table 1-1. pin descriptions (continued) pin names pin type pin no. pin description p10.0 p10.1 p10.2 p10.3 p10.4 p10.5 p10.6 p10.7 i/o 50 51 52 53 54 55 56 57 i/o port with bit-programmable pins; schmitt trigger input or push-pull, open-drain output and software assignable pull-up;
product overview s3 c852b/P852B (p reliminary s pec ) 1- 10 pin circuits in v dd p-channel n-channel figure 1-3. pin circuit type 1 in v dd pull-up resistor schmitt trigger figure 1-4. pin circuit type 2 ( reset reset ) v dd output disable data pull-up resistor v dd noise filter pull-up enable external interrupt input input v ss i/o figure 1-5. pin circuit type 3 (port 0)
s3c852b/P852B (p reliminary s pec ) product overview 1- 11 pin circuits ( continued) v dd output disable data pull-up resistor v dd pull-up enable analog input v ss open-drain select digital or analog input + - ref digital input i/o figure 1-6. pin circuit type 4 (port 1.0-port 1.3)
product overview s3 c852b/P852B (p reliminary s pec ) 1- 12 pin circuits (c ontinued ) v dd output disable data pull-up resistor v dd pull-up enable input v ss open-drain m u x select external interface ( pm, dm, rd, wr ) i/o figure 1-7. pin circuit type 5 (port 3) v dd output disable data pull-up resistor v dd pull-up enable input v ss open-drain m u x select external interface ( a 0-a7, a8-a15, d0-d7) i/o figure 1-8. pin circuit type 6 (port 4, 5, 6)
s3c852b/P852B (p reliminary s pec ) address spaces 2- 1 2 address spaces overview the s3c852b microcontroller has four types of address space: ? internal program memory (rom) ? internal register file ? internal data memory (ram) a 16-bit address bus supports both external program memory and external data memory operations. special instructions and related internal logic determine when the 16-bit bus carries addresses for external program memory or for external data memory locations. sam87rc bus architecture therefore supports up to 64 k bytes of program memory (rom). using the external interface, you can address up to 64 k bytes of program memory and 64 k bytes of data memory simultaneously. these spaces can be combined or kept separate. the s3c852b/P852B microcontroller has 1808-byte registers in its internal register file. a separate 8 -bit register bus carries addresses and data between the cpu and the internal register file. the most of these registers can serve as either a source or destination address, or as accumulators for data memory operations. special 85 bytes of the register file are used for working registers, system and peripheral control functions.
address spaces s3c85 2b/P852B (p reliminary s pec ) 2- 2 program memory (rom) normal operating mode (internal rom) the s3c852b/P852B has 64 k bytes (locations 0h?ffffh) of internal mask-programmable program memory. for normal (internal rom) operation, the ea pin should be connected to v ss . the first 256 bytes of the rom (0h?0ffh) are reserved for interrupt vector addresses. unused locations in this address range can be used as normal program memory. if you do use the vector address area to store program code, be careful to avoid overwriting vector addresses stored in these locations. the program reset address in the rom is 0100h. rom-less operating mode (external rom) for special applications that require external program memory, you can use the rom-less operating mode to configure an up to 64-kbyte area externally. access to the internal 64-kbyte program memory area is disabled in rom-less mode. mode selection (internal rom or rom-less) depends on the voltage that is applied to the ea pin during a power- on reset operation: ? when 0 v is applied to the ea pin, the s3c852b/P852B's internal rom is configured normally and the 64- kbyte space (0h?ffffh) is addressed. ? when 5 v is applied to the ea pin, the s3c852b/P852B operates in rom-less mode. external memory locations 0000h?ffffh are accessed over the 16 -bit address/8-bit data bus, then the internal 64-kbyte program memory area is disabled. when 5 v is applied to the ea pin during a power-on reset, the external peripheral interface is automatically configured as follows: ? the address and data lines for the external interface are configured at port 4, port 5 and port 6 (the control registers p4con, p5con and p6con are set to their initial value for external interface). ? p3afs register values are set to configure the interface signals ( pm , dm , rd , and wr ) at port 3.0?port 3.3.
s3c852b/P852B (p reliminary s pec ) address spaces 2- 3 (decimal) 65,535 256 (hex) ffffh 0100h 0000h 0 program start rom-less operating mode (decimal) 65,535 256 (hex) ffffh 0100h 0000h 0 interrupt vector area 64-kbyte internal program memory area program start normal operating mode interrupt vector area 64-kbyte external program memory area figure 2-1. program memory address space
address spaces s3c85 2b/P852B (p reliminary s pec ) 2- 4 register architecture in the s3c852b/P852B implementation, the upper 64 bytes of the 256-byte physical register file is logically divided into two 64 -byte areas, called set 1 and set 2 . set 1 is further divided into bank 0(64-byte registers) and bank 1(32-byte registers). in addition, the 256-byte area is logically expanded into seven separately addressable register pages, page 0?page 6. this gives a giving a total of 1792 addressable general-purpose registers. the 8-bit register bus can address up to 256 bytes (0h?ffh) in any one of the seven pages. the register file area is, therefore, 1888-bytes, calculated as 256 bytes 7 (pages 0?6 in set 2) + 64 bytes (bank 0 in set 1) + 32 bytes (bank 1 in set 1). however, because 11-bytes are not mapped in set 1, the total number of addressable 8- bit registers is 1877. of these 1877 registers, 69-bytes are for cpu, system control, peripheral control and data registers, 16 bytes are used as a shared working registers, and 1792-byte registers are for general-purpose use. you can always address set 1 register locations, regardless of which of the seven register pages is currently selected. set 1 locations can, however, only be addressed using register addressing modes. the extension of the physical register space into separately addressable areas (sets, banks, and pages) is supported by various addressing mode restrictions, the select bank instructions, sb0 and sb1, and the register page pointer (pp). specific register types and the area (in bytes) that they occupy in the register file are summarized in table 2-1. table 2-1. s3c852b register type summary register type number of bytes cpu and system control registers 19 peripheral, i/o, and clock control/data registers 50 reserved working register area 16 general-purpose registers 1,792 total addressable bytes 1,877
s3c852b/P852B (p reliminary s pec ) address spaces 2- 5 set 2 ffh fch e0h d0h c0h set 1 bank 0 ffh fch e0h set 1 bank 1 system and peripheral control registers (register addressing mode) working registers (working register addressing mode only) system registers (register addressing mode) system and peripheral control registers (register addressing mode) set 2 set 2 set 2 set 2 set 2 ffh ffh ffh ffh ffh ffh c0h 00h bfh page (00h) page (06h) ffh 192 bytes set 2 general purpose data registers (indirect register or indexed addressing mode and stack operations) prime data registers (all addressing modes) 256 bytes ffh figure 2-2. internal register file organization
address spaces s3c85 2b/P852B (p reliminary s pec ) 2- 6 register page pointer (pp) in the s3c852b/P852B, the physical area of the internal register file is logically expanded by the additional of seven register pages. page addressing is controlled by the register page pointer (pp, dfh). see figure 2-3. following a reset, the page pointer?s source value (lower nibble) and destination value (upper nibble) are always ?0000?, automatically selecting page 0 as the source and destination page for register addressing. whenever you select a different page, the current 256-byte address area (0h?ffh) is logically switched with the address range of the new page (see section 4 "pp" register for more information). register page pointer (pp) dfh ,set 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 destination register page selection bits: 0000 destination: page 0 source register page selection bits: 0000 source: page 0 note: in the s3c852b microcontroller, page 0h-6h are implemented. a hardware reset operation writes the 4-bit destination and source values shown above to the register page pointer. these values should be modified to address other pages. figure 2-3. register page pointer (pp) register set 1 the term set 1 refers to the upper 64 bytes of the register file, locations c0h?ffh. this area can be accessed at any time, regardless of which page is currently selected. the upper 32-byte area of this 64-byte space is divided into two 32-byte register banks, called bank 0 and bank 1 . you use the select register bank instructions, sb0 or sb1, to address one bank or the other. a reset operation automatically selects bank 0 addressing. the lower 32-byte area of set 1 is not banked. this area contains 16 bytes for mapped system registers (d0h? dfh) and a 16-byte common area (c0h?cfh) for working register addressing. registers in set 1 are directly accessible at all times using the register addressing mode. the 16-byte working register area can only be accessed using working register addressing, however. working register addressing is a function of register addressing mode (see section 3, "addressing modes," for more information).
s3c852b/P852B (p reliminary s pec ) address spaces 2- 7 register set 2 the same 64-byte physical space that is used for set 1 register locations c0h?ffh is logically duplicated to add another 64 bytes. this expanded area of the register file is called set 2 . for the s3c852b/P852B, the set 2 address range (c0h?ffh) is accessible on pages 0?6. the logical division of set 1 and set 2 is maintained by means of addressing mode restrictions: while you can access set 1 using register addressing mode only, you can only use register indirect addressing mode or indexed addressing mode to access set 2. prime register space the lower 192 bytes (00h?bfh) of the s3c852b/P852B's eight 256 -byte register pages is called prime register area. prime registers can be accessed using any of the seven addressing modes (see section 3, "addressing modes"). the prime register area on page 0 is immediately addressable following a reset. in order to address prime registers on pages 1, 2, 3, 4, 5 or 6, you must set the register page pointer (pp) to the appropriate source and destination values. set 2 ffh fch e0h d0h c0h set 1 bank 0 area not mapped bank 1 peripheral and i/o general-purpose cpu and system control set 2 set 2 set 2 set 2 set 2 ffh c0h 00h prime space set 2 page 0 page 6 figure 2-4. map of set 1, set 2, and prime register spaces
address spaces s3c85 2b/P852B (p reliminary s pec ) 2- 8 working registers instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. when 4-bit working register addressing is used, the 256-byte register file can be viewed by the programmer as consisting of 32 8-byte register groups or "slices." each slice consists of eight 8-bit registers. using the two 8-bit register pointers, rp1 and rp0, two working register slices can be selected at any one time to form a 16-byte working register block. using the register pointers, you can move this 16-byte register block anywhere in the addressable register file, except for the set 2 area. the terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces: ? one working register slice is 8 bytes (eight 8-bit working registers; r0?r7 or r8?r15) ? one working register block is 16 bytes (sixteen 8-bit working registers; r0?r15) all of the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. this makes it possible for each register pointer to point to one of the 24 slices in the register file. the base addresses for the two selected 8-byte register slices are contained in register pointers rp0 and rp1. after a reset, rp0 and rp1 always point to the 16-byte common area in set 1 (c0h?cfh). each register pointer points to one 8-byte slice of the register space, selecting a total 16-byte working register block. 1 1 1 1 1 x x x rp1 (registers r8-r15) rp0 (registers r0-r7) slice 32 slice 31 ~ ~ cfh c0h ffh f8h f7h f0h fh 8h 7h 0h slice 2 slice 1 10h set 1 only 0 0 0 0 0 x x x figure 2-5. 8-byte working register areas (slices)
s3c852b/P852B (p reliminary s pec ) address spaces 2- 9 using the register pointers register pointers rp0 and rp1 are mapped to addresses d6h and d7h in set 1. they are used to select two movable 8-byte working register slices in the register file. after a reset, they point to the working register common area: rp0 points to addresses c0h?c7h, and rp1 points to addresses c8h?cfh. to change a register pointer value, you load a new value to rp0 and/or rp1 using an srp or ld instruction (see figures 2-6 and 2-7). with working register addressing, you can only access those locations that are pointed to by the register pointers. please note that you cannot use the register pointers to select working register area in set 2, c0h?ffh, because these locations are accessible only using the indirect register or indexed addressing modes. the selected 16-byte working register block usually consists of two contiguous 8-byte slices. as a general programming guideline, we recommend that rp0 point to the "lower" slice and rp1 point to the "upper" slice (see figure 2-6). in some cases, you may need to define working register areas in different (non-contiguous) areas of the register file. in figure 2-7, rp0 points to the "upper" slice and rp1 to the "lower" slice. because a register pointer can point to the either of the two 8-byte slices in the working register block, definition of the working register area is very flexible. f f programming tip ? setting the register pointers srp #70h ; rp0 ? 70h, rp1 ? 78h srp1 #48h ; rp0 ? no change, rp1 ? 48h srp0 #0a0h ; rp0 ? a0h, rp1 ? no change clr rp0 ; rp0 ? 00h, rp1 ? no change ld rp1,#0f8h ; rp0 ? no change, rp1 ? 0f8h
address spaces s3c85 2b/P852B (p reliminary s pec ) 2- 10 fh (r15) 0h (r0) 16-byte contiguous working register block register file contains 32 8-byte slices rp0 rp1 8h 7h 0 0 0 0 1 x x x 0 0 0 0 0 x x x 8-byte slice 8-byte slice figure 2-6. contiguous 16-byte working register block 16-byte contiguous working register block register file contains 32 8-byte slices 0 0 0 0 0 x x x rp1 1 0 1 1 0 x x x rp0 0h (r0) 7h (r15) f0h (r0) f7h (r7) 8-byte slice 8-byte slice figure 2-7. non-contiguous 16-byte working register block
s3c852b/P852B (p reliminary s pec ) address spaces 2- 11 calculate the sum of registers 80h?85h using the register pointer. the register addresses 80h through 85h contains the values 10h, 11h, 12h, 13h, 14h, and 15 h, respectively: srp0 #80h ; rp0 ? 80h add r0,r1 ; r0 ? r0 + r1 adc r0,r2 ; r0 ? r0 + r2 + c adc r0,r3 ; r0 ? r0 + r3 + c adc r0,r4 ; r0 ? r0 + r4 + c adc r0,r5 ; r0 ? r0 + r5 + c the sum of these six registers, 6fh, is located in the register r0 (80h). the instruction string used in this example takes 12 bytes of instruction code and its execution time is 24 cycles. if the register pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used: add 80h,81h ; 80h ? (80h) + (81h) adc 80h,82h ; 80h ? (80h) + (82h) + c adc 80h,83h ; 80h ? (80h) + (83h) + c adc 80h,84h ; 80h ? (80h) + (84h) + c adc 80h,85h ; 80h ? (80h) + (85h) + c now, the sum of the six registers is also located in register 80h. however, this instruction string takes 15 bytes of instruction code instead of 12 bytes, and its execution time is 30 cycles instead of 24 cycles.
address spaces s3c85 2b/P852B (p reliminary s pec ) 2- 12 register addressing the sam8 register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. the register (r) addressing mode, in which the operand value is the content of a specific register or register pair, can be used to access all locations in the register file except for set 2. for working register addressing, the register pointers rp0 and rp1 are used to select a specific register within a selected 16-byte working register area. to increase the speed of context switches in an application program, you can use the register pointers to dynamically select different 8 -byte "slices" of the register file as the program's active working register space. registers are addressed either as a single 8-bit register or as a paired 16-bit register. in 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register. msb rn lsb rn+1 n = even address figure 2-8. 16-bit register pairs
s3c852b/P852B (p reliminary s pec ) address spaces 2- 13 rp1 rp0 register pointers 00h all addressing modes page 0 indirect register, indexed addressing modes page 0 register addressing only can be pointed by register pointer ffh e0h bfh control registers system registers special-purpose registers d0h c0h bank 1 bank 1 each register pointer (rp) can independently point to one of the 24 8-byte "slices" of the register file (other than set 2). after a reset, rp0 points to locations c0h-c7h and rp1 to locations c8h-cfh (that is, to the common working register area). ffh c0h set 2 prime registers cfh general-purpose register d6h d7h figure 2-9. register file addressing
address spaces s3c85 2b/P852B (p reliminary s pec ) 2- 14 common working register area (c0h?cfh) after a reset, register pointers rp0 and rp1 automatically select two 8-byte register slices in set 1, locations c0h?cfh, as the active 16-byte working register block: rp0 ? c0h?c7h rp1 ? c8h?cfh this 16-byte address range is called the common area . you can use common area registers as working registers for operations that address locations on different pages in the register file. page 0 set 2 ffh fch e0h cfh c0h set 1 following a hardware reset, register pointers rp0 and rp1 point to the common working register area, locations c0h-cfh. rp0 = rp1 = 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 dfh set 2 set 2 set 2 set 2 set 2 ffh c0h 00h prime space set 2 page 6 figure 2-10. common working register area
s3c852b/P852B (p reliminary s pec ) address spaces 2- 15 f f programming tip ? addressing the common working register area as the following examples show, you should access working registers in the common area, locations c0h?cfh, using working register addressing mode only. example 1: ld 0c2h,40h ; invalid addressing mode! use working register addressing instead: srp #0c0h ld r2,40h ; r2 (c2h) ? the value in location 40h example 2: add 0c3h,#45h ; invalid addressing mode! use working register addressing instead: srp #0c0h add r3,#45h ; r3 (c3h) ? r3 + 45h
address spaces s3c85 2b/P852B (p reliminary s pec ) 2- 16 4-bit working register addressing each register pointer defines a movable 8-byte slice of working register space. the address information stored in a register pointer serves as an addressing "window" that enables instructions to access working registers very efficiently using short 4-bit addresses. when an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address: ? the high-order bit of the 4-bit address selects one of the register pointers ("0" selects rp0; "1" selects rp1); ? the five high-order bits in the register pointer select an 8-byte slice of the register space; ? the three low-order bits of the 4-bit address select one of the eight registers in the slice. as shown in figure 2-11, the net effect of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. as long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice. figure 2-12 shows a typical example of 4-bit working register addressing: the high-order bit of the instruction 'inc r6' is "0", which selects rp0. the five high-order bits stored in rp0 (01110b) are concatenated with the three low-order bits of the instruction's 4-bit address (110b) to produce the register address 76h (01110110b).
s3c852b/P852B (p reliminary s pec ) address spaces 2- 17 together they create an 8-bit register address register pointer provides five high-order bits address opcode selects rp0 or rp1 rp1 rp0 4-bit address procides three low-order bits figure 2-11. 4-bit working register addressing register address (76h) rp0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 r6 0 1 1 0 1 1 1 0 selects rp0 instruction: 'inc r6' opcode rp1 0 1 1 1 1 0 0 0 figure 2-12. 4-bit working register addressing example
address spaces s3c85 2b/P852B (p reliminary s pec ) 2- 18 8-bit working register addressing you can also use 8-bit working register addressing to access registers in a selected working register area. in order to initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value 1100b. this 4-bit value (1100b) indicates that the remaining four bits have the same effect as 4-bit working register addressing. as shown in figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4 -bit addressing: bit 3 selects either rp0 or rp1, which then supplies the five high-order bits of the final address, and the three low-order bits of the complete address are provided by the original instruction. figure 2-14 shows an example of 8-bit working register addressing: the four high-order bits of the instruction address (1100b) specify 8-bit working register addressing. the fourth bit ("1") selects rp1 and the five high-order bits in rp1 (10100b) become the five high-order bits of the register address. the three low-order bits of the register address (011) are provided by the three low-order bits of the 8-bit instruction address. together, the five address bits from rp1 and the three address bits from the instruction comprise the complete register address, 0abh (10100011b). 8-bit physical address register pointer provides five high-order bits address selects rp0 or rp1 rp1 rp0 three low- order bits 8-bit logical address these address bits indicate 8-bit working register addressing 1 1 0 0 figure 2-13. 8-bit working register addressing
s3c852b/P852B (p reliminary s pec ) address spaces 2- 19 8-bit address form instruction 'ld r11, r2' rp0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 selects rp1 r11 register address (0abh) rp1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 specifies working register addressing figure 2-14. 8-bit working register addressing example
address spaces s3c85 2b/P852B (p reliminary s pec ) 2- 20 system and user stacks ks88-series microcontrollers can be programmed to use system stack for subroutine calls, returns, interrupts, and to store data. the push and pop instructions are used to control system stack operations. the sam8 architecture supports stack operations in the internal register file as well as in external data memory. to select an internal or external stack area, you set bit 1 of the external memory timing register, emt.1 to the appropriate value. stack operations return addresses for procedure calls and interrupts and data are stored on the stack. the contents of the pc are saved to stack by a call instruction and restored by the ret instruction. when an interrupt occurs, the contents of the pc and the flags register are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address is always decremented before a push operation and incremented after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2-15. stack contents after a call instruction stack contents after an interrupt top of stack flags pch pcl pcl pch top of stack low address high address figure 2-15. stack operations user-defined stacks you can freely define stacks in the internal register file as data storage locations. the instructions pushui, pushud, popui, and popud support user-defined stack operations. these instructions cannot address external memory locations. only push and pop instructions can be used for an externally defined stack.
s3c852b/P852B (p reliminary s pec ) address spaces 2- 21 stack pointers (spl, sph) register locations d8h and d9h contain the 16-bit stack pointer (sp) that is used for system stack operations. the most significant byte of the sp address, sp15?sp8, is stored in the sph register (d8h); the least significant byte, sp7?sp0, is stored in the spl register (d9h). after a reset, the sp value is undetermined. if only internal memory space is implemented, the spl must be initialized to an 8-bit value in the range 00h? ffh; the sph register is not needed (and can be used as a general-purpose register, if needed). if external memory is implemented, both spl and sph must be initialized with a full 16-bit address. when the spl register contains the only stack pointer value (that is, when it points to a system stack in the register file), the sph register can be used as a general-purpose data register. however, if an overflow or underflow condition occurs as the result of incrementing or decrementing the stack address in the spl register during normal stack operations, the value in the spl register will overflow (or underflow) to the sph register, overwriting any other data that is currently stored there. to avoid overwriting data in the sph register, you can initialize the spl value to ffh instead of 00h. stack operation page is in only page 0 , regardless the processing page. f f programming tip ? standard stack operations using push and pop the following example shows you how to perform stack operations in the internal register file using push and pop instructions: ld spl,#0ffh ; spl ? ffh (normally, the spl is set to 0ffh by the ? ; initialization routine) ? ? push pp ; stack address 0feh ? pp push rp0 ; stack address 0fdh ? rp0 push rp1 ; stack address 0fch ? rp1 push r3 ; stack address 0fbh ? r3 ? ? ? pop r3 ; r3 ? stack address 0fbh pop rp1 ; rp1 ? stack address 0fch pop rp0 ; rp0 ? stack address 0fdh pop pp ; pp ? stack address 0feh
address spaces s3c85 2b/P852B (p reliminary s pec ) 2- 22 notes
s3c852b/P852B (p reliminary s pec ) addressing modes 3- 1 3 addressing modes overview instructions that are stored in program memory are fetched for execution using the program counter. instructions indicate the operation to be performed and the data to be operated on. addressing mode is the method used to determine the location of the data operand. the operands specified in sam87rc instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the sam87rc instruction set supports seven explicit addressing modes. not all of these addressing modes are available for each instruction. the addressing modes and their symbols are as follows: ? register (r) ? indirect register (ir) ? indexed (x) ? direct address (da) ? indirect address (ia) ? relative address (ra) ? immediate (im)
addressing modes s3 c852b/P852B (p reliminary s pec ) 3- 2 register addressing mode (r) in register addressing mode, the operand is the content of a specified register or register pair (see figure 3-1). working register addressing differs from register addressing because it uses a register pointer to specify an 8 -byte working register space in the register file and an 8-bit register within that space (see figure 3-2). dst value used in instruction execution opcode operand 8-bit register file address point to one rigister in register file one-operand instruction (example) sample instruction: dec cntr ; where cntr is the label of an 8-bit register address program memory register file figure 3-1. register addressing dst opcode 4-bit working register points to the woking register (1 of 8) two-operand instruction (example) sample instruction: add r1, r2 ; where r1 and r2 are registers in the currently selected working register area. program memory register file src 3 lsbs rp0 or rp1 selected rp points to start of working register block operand msb points to rp0 ot rp1 figure 3-2. working register addressing
s3c852b/P852B (p reliminary s pec ) addressing modes 3- 3 indirect register addressing mode (ir) in indirect register (ir) addressing mode, the content of the specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, to program memory (rom), or to an external memory space (see figures 3-3 through 3- 6). you can use any 8-bit register to indirectly address another register. any 16-bit register pair can be used to indirectly address another memory location. you cannot, however, access locations c0h?ffh in set 1 using indirect register addressing mode. dst address of operand used by instruction opcode address 8-bit register file address points to one rigister in register file one-operand instruction (example) sample instruction: rl @shift ; where shift is the label of an 8-bit register address program memory register file value used in instruction execution operand figure 3-3. indirect register addressing to register file
addressing modes s3 c852b/P852B (p reliminary s pec ) 3- 4 indirect register addressing mode (c ontinued ) dst opcode pair points to register pair example instruction references program memory sample instructions: call @rr2 jp @rr2 program memory register file value used in instruction operand register program memory 16-bit address points to program memory figure 3-4. indirect register addressing to program memory
s3c852b/P852B (p reliminary s pec ) addressing modes 3- 5 indirect register addressing mode (c ontinued ) dst opcode address 4-bit working register address points to the woking register (1 of 8) sample instruction: or r3, @r6 program memory register file src 3 lsbs value used in instruction operand selected rp points to start fo woking register block rp0 or rp1 msb points to rp0 or rp1 ~ ~ ~ ~ figure 3-5. indirect working register addressing to register file
addressing modes s3 c852b/P852B (p reliminary s pec ) 3- 6 indirect register addressing mode (c oncluded ) dst opcode 4-bit working register address sample instructions: lcd r5,@rr6 ; program memory access lde r3,@rr0 ; external data memory access lde @rr4, r8 ; external data memory access program memory register file src value used in instruction operand example instruction references either program memory or data memory program memory or data memory next 2-bit point to working register pair (1 of 4) lsb selects register pair 16-bit address points to program memory or data memory rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block figure 3-6. indirect working register addressing to program or data memory
s3c852b/P852B (p reliminary s pec ) addressing modes 3- 7 indexed addressing mode (x) indexed (x) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see figure 3-7). you can use indexed addressing mode to access locations in the internal register file or in external memory. you cannot, however, access locations c0h?ffh in set 1 using indexed addressing mo de. in short offset indexed addressing mode, the 8 -bit displacement is treated as a signed integer in the range ?128 to +127. this applies to external memory accesses only (see figure 3-8.) for register file addressing, an 8 -bit base address provided by the instruction is added to an 8-bit offset contained in a working register. for external memory accesses, the base address is stored in the working register pair designated in the instruction. the 8-bit or 16-bit offset given in the instruction is then added to the base address (see figure 3-9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program memory and for external data memory, when implemented. dst/src opcode two-operand instruction example point to one of the woking register (1 of 8) sample instruction: ld r0, #base[r1] ; where base is an 8-bit immediate value program memory register file x 3 lsbs value used in instruction operand index base address rp0 or rp1 selected rp points to start of working register block ~ ~ ~ ~ + msb points to rp0 or rp1 figure 3-7. indexed addressing to register file
addressing modes s3 c852b/P852B (p reliminary s pec ) 3- 8 indexed addressing mode (c ontinued ) register file operand program memory or data memory point to working register pair (1 of 4) lsb selects 16-bit address added to offset rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block dst/src opcode program memory x offset 4-bit working register address sample instructions: ldc r4, #04h[rr2] ; the values in the program address (rr2 + 04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 2 bits register pair value used in instruction 8-bits 16-bits 16-bits + ~ ~ figure 3-8. indexed addressing to program or data memory with short offset
s3c852b/P852B (p reliminary s pec ) addressing modes 3- 9 indexed addressing mode (c oncluded ) register file operand program memory or data memory point to working register pair lsb selects 16-bit address added to offset rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block sample instructions: ldc r4, #1000h[rr2] ; the values in the program address (rr2 + 1000h) are loaded into register r4. lde r4,#1000h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 2 bits register pair value used in instruction 16-bits 16-bits 16-bits dst/src opcode program memory x offset 4-bit working register address offset + ~ ~ figure 3-9. indexed addressing to program or data memory
addressing modes s3 c852b/P852B (p reliminary s pec ) 3- 10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16-bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the pc whenever a jp or call instruction is executed. the ldc and lde instructions can use direct address mode to specify the source or destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. sample instructions: ldc r5,1234h ; the values in the program address (1234h) are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external program memory is accessed. dst/src opcode program memory "0" or "1" lower address byte lsb selects program memory or data memory: "0" = program memory "1" = data memory memory address used upper address byte program or data memory figure 3-10. direct addressing for load instructions
s3c852b/P852B (p reliminary s pec ) addressing modes 3- 11 direct address mode (c ontinued ) opcode program memory lower address byte memory address used upper address byte sample instructions: jp c,job1 ; where job1 is a 16-bit immediate address call display ; where display is a 16-bit immediate address next opcode figure 3-11. direct addressing for call and jump instructions
addressing modes s3 c852b/P852B (p reliminary s pec ) 3- 12 indirect address mode (ia) in indirect address (ia) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. the selected pair of memory locations contains the actual address of the next instruction to be executed. only the call instruction can use the indirect address mode. because the indirect address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros. current instruction program memory locations 0-255 program memory opcode dst lower address byte upper address byte next instruction lsb must be zero sample instruction: call #40h ; the 16-bit value in program memory addresses 40h and 41h is the subroutine start address. figure 3-12. indirect addressing
s3c852b/P852B (p reliminary s pec ) addressing modes 3- 13 relative address mode (ra) in relative address (ra) mode, a two's-complement signed displacement between ? 128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the instruction immediately following the current instruction. several program control instructions use the relative address mode to perform conditional jumps. the instructions that support ra addressing are btjrf, btjrt, djnz, cpije, cpijne, and jr. opcode program memory displacement program memory address used sample instructions: jr ult,$+offset ; where offset is a value in the range +127 to -128 next opcode + signed displacement value current instruction current pc value figure 3-13. relative addressing
addressing modes s3 c852b/P852B (p reliminary s pec ) 3- 14 immediate mode (im) in immediate (im) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. the operand may be one byte or one word in length, depending on the instruction used. immediate addressing mode is useful for loading constant values into registers. (the operand value is in the instruction) opcode sample instruction: ld r0,#0aah program memory operand figure 3-14. immediate addressing
s3c852b/P852B (p reliminary s pec ) control registers 4- 1 4 control registers overview in this section, detailed descriptions of the s3c852b/P852B control registers are presented in an easy-to-read format. these descriptions will help familiarize you with the mapped locations in the register file. you can also use them as a quick-reference source when writing application programs. system and peripheral registers are summarized in tables 4-1, 4-2, and 4-3. figure 4-1 illustrates the important features of the standard register description format. cid registers are mapped to set 2 register page 8. control register descriptions are arranged in alphabetical order according to register mnemonic. more information about control registers is presented in the context of the various peripheral hardware descriptions in part ii of this manual.
control registers s 3c852b/P852B (p reliminary s pec ) 4- 2 table 4-1. set 1, bank 0 registers register name mnemonic address r/w reset values(bit) decimal hex 7 6 5 4 3 2 1 0 timer 0 counter t0cnt 208 d0h r 0 0 0 0 0 0 0 0 timer 0 data register t0data 209 d1h r/w 1 1 1 1 1 1 1 1 timer 0 control register t0con 210 d2h r/w 0 0 0 0 0 0 0 0 basic timer control register btcon 211 d3h r/w 0 0 0 0 0 0 0 0 clock control register clkcon 212 d4h r/w 0 0 0 0 0 0 0 0 system flags register flags 213 d5h r/w x x x x x x 0 0 register pointer 0 rp0 214 d6h r/w 1 1 0 0 0 ? ? ? register pointer 1 rp1 215 d7h r/w 1 1 0 0 1 ? ? ? stack pointer (high byte) sph 216 d8h r/w x x x x x x x x stack pointer (low byte) spl 217 d9h r/w x x x x x x x x instruction pointer (high byte) iph 218 dah r/w x x x x x x x x instruction pointer (low byte) ipl 219 dbh r/w x x x x x x x x interrupt request register irq 220 dch r 0 0 0 0 0 0 0 0 interrupt mask register imr 221 ddh r/w x x x x x x x x system mode register sym 222 deh r/w 0 ? ? x x x 0 0 register page pointer pp 223 dfh r/w 0 0 0 0 0 0 0 0 port 0 data register p0 224 e0h r/w 0 0 0 0 0 0 0 0 port 1 data register p1 225 e1h r/w 0 0 0 0 0 0 0 0 port 2 data register p2 226 e2h r/w 0 0 0 0 0 0 0 0 port 3 data register p3 227 e3h r/w 0 0 0 0 0 0 0 0 port 4 data register p4 228 e4h r/w 0 0 0 0 0 0 0 0 port 5 data register p5 229 e5h r/w 0 0 0 0 0 0 0 0 port 6 data register p6 230 e6h r/w 0 0 0 0 0 0 0 0 port 0 interrupt control register p0int 231 e7h r/w ? 0 0 0 0 0 0 0 port 0 interrupt pending register p0pnd 232 e8h r/w ? 0 0 0 0 0 0 0 port 0 interrupt state register p0sta 233 e9h r/w ? 0 0 0 0 0 0 0 port 0 control register(high byte) p0conh 234 eah r/w 0 0 0 0 0 0 0 0 port 0 control register(low byte) p0conl 235 ebh r/w 0 0 0 0 0 0 0 0 port 1 control register(high byte) p1conh 236 ech r/w 0 0 0 0 0 0 0 0 port 1 control register(low byte) p1conl 237 edh r/w 0 0 0 0 0 0 0 0 port 1 function select register p1afs 238 eeh r/w - - - - 0 0 0 0 port 2 control register p2con 239 efh r/w 0 0 0 0 0 0 0 0 port 3 control register p3con 241 f1h r/w 0 0 0 0 0 0 0 0 port 3 function select register p3afs 242 f2h r/w ? ? ? ? 0 0 0 0 port 4 control register p4con 243 f3h r/w 0 0 0 0 0 0 0 0 port 5 control register p5con 244 f4h r/w 0 0 0 0 0 0 0 0
s3c852b/P852B (p reliminary s pec ) control registers 4- 3 table 4-1. set 1, bank 0 registers (continued) register name mnemonic address r/w reset values(bit) decimal hex 7 6 5 4 3 2 1 0 port 6 control register p6con 245 f5h r/w 0 0 0 0 0 0 0 0 location f6h-f7h is not mapped. clock output mode register clkmod 248 f8h r/w ? ? ? ? ? 0 0 0 interrupt pending register intpnd 249 f9h r/w ? ? ? ? ? 0 0 0 oscillator control register osccon 250 fah r/w ? ? ? ? 0 0 ? 0 stop control register stpcon 251 fbh r/w 0 0 0 0 0 0 0 0 location fch is not mapped. basic timer counter btcnt 253 fdh r x x x x x x x x external memory timing register emt 254 feh r/w ? 1 1 1 1 1 0 ? interrupt priority register ipr 255 ffh r/w x x x x x x x x table 4-2. set 1, bank 1 registers register name mnemonic address r/w reset values(bit) decimal hex 7 6 5 4 3 2 1 0 timer a counter tacnt 224 e0h r 0 0 0 0 0 0 0 0 timer b counter tbcnt 225 e1h r 0 0 0 0 0 0 0 0 timer a data register tadata 226 e2h r/w 1 1 1 1 1 1 1 1 timer b data register tbdata 227 e3h r/w 1 1 1 1 1 1 1 1 timer a control register tacon 228 e4h r/w 0 0 0 0 0 0 0 0 timer b control register tbcon 229 e5h r/w 0 0 0 0 0 0 0 0 w/t control register wtcon 230 e6h r/w 0 0 0 0 0 0 0 0 sio data register siodata 234 eah r/w 1 1 1 1 1 1 1 1 sio control register siocon 235 ebh r/w 0 0 0 0 0 0 0 0 sio pre-scaler register siops 236 ech r/w 0 0 0 0 0 0 0 0 port 7 data register p7 237 edh r/w 0 0 0 0 0 0 0 0 a/d data register(high byte) addatah 242 f2h r x x x x x x x x a/d data register(low byte) addatal 243 f3h r ? ? ? ? ? ? x x a/d control register adcon 244 f4h r/w 0 0 0 0 0 0 0 0 port 8 data register p8 245 f5h r/w 0 0 0 0 0 0 0 0 port 9 data register p9 246 f6h r/w 0 0 0 0 0 0 0 0 port 10 data register p10 247 f7h r/w 0 0 0 0 0 0 0 0 port 7 control register (high byte) p7conh 248 f8h r/w 0 0 0 0 0 0 0 0 port 7 control register (low byte) p7conl 249 f9h r/w 0 0 0 0 0 0 0 0 port 8 control register (high byte) p8conh 250 fah r/w 0 0 0 0 0 0 0 0 port 8 control register (low byte) p8conl 251 fbh r/w 0 0 0 0 0 0 0 0 port 9 control register (high byte) p9conh 252 fch r/w 0 0 0 0 0 0 0 0 port 9 control register (low byte) p9conl 253 fdh r/w 0 0 0 0 0 0 0 0 port 10 control register (high byte) p10conh 254 feh r/w 0 0 0 0 0 0 0 0 port 10 control register (low byte) p10conl 255 ffh r/w 0 0 0 0 0 0 0 0
control registers s 3c852b/P852B (p reliminary s pec ) 4- 4 flags - system flags register .7 carry flag (c) .6 zero flag (z) .5 bit identifier reset reset value read/write bit addressing mode r = read-only w = write-only r/w = read/write '-' = not used type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) reset value notation: '-' = not used 'x' = undetermined value '0' = logic zero '1' = logic one bit number(s) that is/are appended to the register name for bit addressing name of individual bit or related bits register name register id sign flag (s) 0 operation does not generate a carry or borrow condition 0 operation generates carry-out or borrow into high-order bit 7 0 operation result is a non-zero value 0 operation result is zero 0 operation generates positive number (msb = "0") 0 operation generates negative number (msb = "1") description of the effect of specific bit settings set 1 register location in the internal register file d5h register address (hexadecimal) .7 .6 .5 x x x r/w r/w r/w register addressing mode only .4 .3 .2 .1 .0 x r/w x r/w x r/w x r/w 0 r/w bit number: msb = bit 7 lsb = bit 0 figure 4-1. register description format
s3c852b/P852B (p reliminary s pec ) control registers 4- 5 adcon ? a/d converter control register f4h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write ? ? r/w r/w r r/w r/w r/w addressing mode register addressing mode only .7 - .6 not used for s3c852b/P852B .5?.4 a/d converter analog input pin selection bits 0 0 adc0 (p1.0) 0 1 adc1 (p1.1) 1 0 adc2 (p1.2) 1 1 adc3 (p1.3) .3 end-of-conversion bit (read-only) (note) 0 a/d conversion operation is in progress 1 a/d conversion operation is complete .2?.1 clock source selection 0 0 fxx/16 0 1 fxx/8 1 0 fxx/4 1 1 fxx/1 .0 start or enable bit 0 disable operation 1 start operation note : this bit is read-only. you can poll adcon.3 to determine internally when an a/d conversion operation has been completed. a reset operation sets adcon.3 to "0".
control registers s 3c852b/P852B (p reliminary s pec ) 4- 6 btcon ? basic timer control register d3h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 watchdog timer function disable code (for reset) 1 0 1 0 disable watchdog timer function any other value enable watchdog timer function .3 and .2 basic timer input clock selection bits 0 0 fxx/4096 0 1 fxx/1024 1 0 fxx/128 1 1 fxx/16 .1 basic timer counter clear bit (1) 0 no effect 1 clear the basic timer counter value .0 clock frequency divider clear bit for basic timer (2) 0 no effect 1 clear divider notes: 1. when you write a ?1? to btcon.1, the basic timer counter value is cleared to ?00h?. immediately following the write operation, the btcon.1 value is automatically cleared to ?0?. 2. when you write a "1" to btcon.0, the corresponding frequency divider is cleared to '00h'. immediately following the write operation, the btcon.0 value is automatically cleared to "0".
s3c852b/P852B (p reliminary s pec ) control registers 4- 7 clkcon ? system clock control register d4h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w ? ? r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 oscillator irq wake-up function enable bit 0 enable irq for main system oscillator wake-up in power-down mode 1 disable irq for main system oscillator wake-up in power-down mode .6 and .5 not used for s3c852b/P852B .4 and .3 cpu clock (system clock) selection bits (1) 0 0 divide by 16 (fx/16) or fxt 0 1 divide by 8 (fx/8) or fxt 1 0 divide by 2 (fx/2) or fxt 1 1 non-divided clock (fx) or fxt .2?.0 not used for s3c852b/P852B note: after a reset, the slowest clock (divided by 16) is selected as the system clock. to select faster clock speeds, load he appropriate values to clkcon.3 and clkcon.4.
control registers s 3c852b/P852B (p reliminary s pec ) 4- 8 clkmod ? clock output mode register f8h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? 0 0 0 read/write ? ? ? ? ? r/w r/w r/w addressing mode register addressing mode only .7?.3 not used for s3c852b/P852B .2 m signal selection bit 0 m signal 1 inversed m signal .1 and .0 output clock selection bits 0 0 fxx 0 1 fxx/2 3 1 0 fxx/2 6 1 1 cpu clock output
s3c852b/P852B (p reliminary s pec ) control registers 4- 9 emt ? external memory timing register feh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? 1 1 1 1 1 0 ? read/write ? ? ? ? ? ? r/w ? addressing mode register addressing mode only .7?.2 not used for s3c852b/P852B .1 stack area selection bit 0 select internal register file area 1 select external data memory area .0 not used for s3c852b/P852B
control registers s 3c852b/P852B (p reliminary s pec ) 4- 10 flags ? system flags register d5h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 carry flag (c) 0 operation does not generate a carry or borrow condition 1 operation generates a carry-out or borrow into high-order bit 7 .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is +127 or 3 ?128 1 operation result is > +127 or < ?128 .3 decimal adjust flag (d) 0 add operation completed 1 subtraction operation completed .2 half-carry flag (h) 0 no carry-out of bit 3 or no borrow into bit 3 by addition or subtraction 1 addition generated carry-out of bit 3 or subtraction generated borrow into bit 3 .1 fast interrupt status flag (fis) 0 cleared automatically during an interrupt return (iret) 1 automatically set to "1" during a fast interrupt service routine .0 bank address selection flag (ba) 0 bank 0 is selected 1 bank 1 is selected
s3c852b/P852B (p reliminary s pec ) control registers 4- 11 imr ? interrupt mask register ddh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w ?- r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 interrupt level 7 (irq7) enable bit; external interrupt int4?int7 0 disable irq7 interrupts 1 enable irq7 interrupts .6 interrupt level 6 (irq6) enable bit; external interrupt int0?int3 0 disable irq6 interrupts 1 enable irq6 interrupts .5 not used for s3c852b/P852B .4 interrupt level 4 (irq4) enable bit; serial data receive/transmit interrupt 0 disable irq4 interrupts 1 enable irq4 interrupts .3 interrupt level 3 (irq3) enable bit; watch timer overflow 0 disable irq3 interrupts 1 enable irq3 interrupts .2 interrupt level 2 (irq2) enable bit; cid block interrupt 0 disable irq2 interrupts 1 enable irq2 interrupts .1 interrupt level 1 (irq1) enable bit; timer a match, timer b match/overflow 0 disable irq1 interrupts 1 enable irq1 interrupts .0 interrupt level 0 (irq0) enable bit; timer 0 match/capture/overflow 0 disable irq0 interrupts 1 enable irq0 interrupts
control registers s 3c852b/P852B (p reliminary s pec ) 4- 12 intpnd ? interrupt pending register f9h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? ? 0 0 0 read/write ? ? ? ? ? r/w r/w r/w addressing mode register addressing mode only .7?.3 not used for s3c852b/P852B .2 timer b match interrupt pending bit 0 no interrupt pending 0 clear pending bit (write) 1 interrupt is pending .1 timer b overflow interrupt pending bit 0 no interrupt pending 0 clear pending bit (write) 1 interrupt is pending .0 timer 0 overflow interrupt pending bit 0 no interrupt pending 0 clear pending bit (write) 1 interrupt is pending
s3c852b/P852B (p reliminary s pec ) control registers 4- 13 iph ? instruction pointer (high byte) dah set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 instruction pointer address (high byte) the high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (ip15?ip8). the lower byte of the ip address is located in the ipl register (dbh). ipl ? instruction pointer (low byte) dbh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 instruction pointer address (low byte) the low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (ip7?ip0). the upper byte of the ip address is located in the iph register (dah).
control registers s 3c852b/P852B (p reliminary s pec ) 4- 14 ipr ? interrupt priority register ffh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w ? r/w r/w r/w r/w r/w addressing mode register addressing mode only .7, .4, and .1 priority control bits for interrupt groups a, b, and c 0 0 0 group priority undefined 0 0 1 b > c > a 0 1 0 a > b > c 0 1 1 b > a > c 1 0 0 c > a > b 1 0 1 c > b > a 1 1 0 a > c > b 1 1 1 group priority undefined .6 interrupt subgroup c priority control bit 0 irq6 > irq7 1 irq7 > irq6 .5 not used for s3c852b/P852B .3 interrupt group b priority control bit 0 irq3 > irq4 1 irq4 > irq3 .2 interrupt group b priority control bit 0 irq2 > (irq3, irq4) 1 (irq3, irq4) > irq2 .0 interrupt group a priority control bit 0 irq0 > irq1 1 irq1 > irq0 note: interrupt group a is irq0 and irq1; interrupt group b is irq3, irq4 and irq2; interrupt group c is irq6, and irq7.
s3c852b/P852B (p reliminary s pec ) control registers 4- 15 irq ? interrupt request register dch set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 ? 0 0 0 0 0 read/write r r ? r r r r r addressing mode register addressing mode only .7 interrupt level 7 (irq7) request pending bit; int4?int7 0 no irq7 interrupt pending 1 irq7 interrupt is pending .6 interrupt level 6 (irq6) request pending bit; int0?int3 0 no irq6 interrupt pending 1 irq6 interrupt is pending .5 not used for s3c852b/P852B .4 interrupt level 4 (irq4) request pending bit; serial data receive/transmit interrupt 0 no irq4 interrupt pending 1 irq4 interrupt is pending .3 interrupt level 3 (irq3) request pending bit; watch timer overflow 0 no irq3 interrupt pending 1 irq3 interrupt is pending .2 interrupt level 2 (irq2) request pending bit; caller id functions 0 no irq2 interrupt pending 1 irq2 interrupt pending .1 interrupt level 1 (irq1) request pending bit; timer a match, timer b match/overflow 0 no irq1 interrupt pending 1 irq1 interrupt is pending .0 interrupt level 0 (irq0) request pending bit; timer 0 match/capture/overflow 0 no irq0 interrupt pending 1 irq0 interrupt is pending
control registers s 3c852b/P852B (p reliminary s pec ) 4- 16 osccon ? oscillator control register fah set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 ? 0 read/write ? ? ? ? r/w r/w ? r/w addressing mode register addressing mode only .7?.4 not used for s3c852b/P852B .3 main system oscillator control bit 0 main system oscillator run 1 main system oscillator stop .2 subsystem oscillator control bit 0 subsystem oscillator run 1 subsystem oscillator stop .1 not used for s3c852b/P852B .0 system clock selection bit 0 select main system clock 1 select subsystem clock
s3c852b/P852B (p reliminary s pec ) control registers 4- 17 p0conh ? port 0 control register (high byte) eah set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 port 0.7/int7 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 not used .5?.4 port 0.6/int6/tb 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 select alternative function for tb .3?.2 port 0.5/int5/ta 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 select alternative function for ta .1?.0 port 0.4/int4/t1ck 0 0 input, schmitt trigger (t1ck) 0 1 input, schmitt trigger, pull-up resistor (t1ck) 1 0 output, push-pull 1 1 not used
control registers s 3c852b/P852B (p reliminary s pec ) 4- 18 p0conl ? port 0 control register(low byte) ebh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 port 0.3/int3/t0/t0cap 0 0 input, schmitt trigger (t0cap) 0 1 input, schmitt trigger, pull-up resistor (t0 cap) 1 0 output, push-pull 1 1 select alternative function for t0 .5?.4 port 0.2/int2/t0ck 0 0 input, schmitt trigger (t0ck) 0 1 input, schmitt trigger, pull-up resistor (t0ck) 1 0 output, push-pull 1 1 not used .3?.2 port 0.1/int1/buz 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 select alternative function for buz .1?.0 port 0.0/int0 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 not used
s3c852b/P852B (p reliminary s pec ) control registers 4- 19 p0int ? port 0 interrupt enable register e7h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 int7/p0.7 interrupt enable bit 0 disable int7 1 enable int7 .6 int6/p0.6 interrupt enable bit 0 disable int6 1 enable int6 .5 int5/p0.5 interrupt enable bit 0 disable int5 1 enable int5 .4 int4/p0.4 interrupt enable bit 0 disable int4 1 enable int4 .3 int3/p0.3 interrupt enable bit 0 disable int3 1 enable int3 .2 int2/p0.2 interrupt enable bit 0 disable int2 1 enable int2 .1 int1/p0.1 interrupt enable bit 0 disable int1 1 enable int1 .0 int0/p0.0 interrupt enable bit 0 disable int0 1 enable int0
control registers s 3c852b/P852B (p reliminary s pec ) 4- 20 p0pnd ? port 0 interrupt pending register e8h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 int7/p0.7 interrupt pending bit 0 int7 interrupt request is not pending 1 int7 interrupt request is pending .6 int6/p0.6 interrupt pending bit 0 int6 interrupt request is not pending 1 int6 interrupt request is pending .5 int5/p0.5 interrupt pending bit 0 int5 interrupt request is not pending 1 int5 interrupt request is pending .4 int4/p0.4 interrupt pending bit 0 int4 interrupt request is not pending 1 int4 interrupt request is pending .3 int3/p0.3 interrupt pending bit 0 int3 interrupt request is not pending 1 int3 interrupt request is pending .2 int2/p0.2 interrupt pending bit 0 int2 interrupt request is not pending 1 int2 interrupt request is pending .1 int1/p0.1 interrupt pending bit 0 int1 interrupt request is not pending 1 int1 interrupt request is pending .0 int0/p0.0 interrupt pending bit 0 int0 interrupt request is not pending 1 int0 interrupt request is pending
s3c852b/P852B (p reliminary s pec ) control registers 4- 21 p0sta ? port 0 interrupt state register e9h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 int7/p0.7 interrupt state setting bit 0 int7 falling edge detection 1 int7 rising edge detection .6 int6/p0.6 interrupt state setting bit 0 int6 falling edge detection 1 int6 rising edge detection .5 int5/p0.5 interrupt state setting bit 0 int5 falling edge detection 1 int5 rising edge detection .4 int4/p0.4 interrupt state setting bit 0 int4 falling edge detection 1 int4 rising edge detection .3 int3/p0.3 interrupt state setting bit 0 int3 falling edge detection 1 int3 rising edge detection .2 int2/p0.2 interrupt state setting bit 0 int2 falling edge detection 1 int2 rising edge detection .1 int1/p0.1 interrupt state setting bit 0 int1 falling edge detection 1 int1 rising edge detection .0 int0/p0.0 interrupt state setting bit 0 int0 falling edge detection 1 int0 rising edge detection
control registers s 3c852b/P852B (p reliminary s pec ) 4- 22 p1afs ? port 1 function select register eeh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? 0 0 0 0 0 0 0 read/write ? r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 not used for s3c852b/P852B .6 port 1.6/ sck sck 0 normal i/o port 1 select alternative function for sck .5 port 1.5/so 0 normal i/o port 1 select alternative function for so .4 port 1.4/si 0 normal i/o port 1 select alternative function for si .3 port 1.3/adc3 0 normal i/o port 1 select analog input function for adc3 .2 port 1.2/adc2 0 normal i/o port 1 select analog input function for adc2 .1 port 1.1/adc1 0 normal i/o port 1 select analog input function for adc1 .0 port 1.0/adc0 0 normal i/o port 1 select analog input function for adc0
s3c852b/P852B (p reliminary s pec ) control registers 4- 23 p1conh ? port 1 control register(high byte) ech set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 port 1.7 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .5?.4 port 1.6 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .3?.2 port 1.5 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .1?.0 port 1.4 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain
control registers s 3c852b/P852B (p reliminary s pec ) 4- 24 p1conl ? port 1 control register(low byte) edh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 port 1.3/adc3 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .5?.4 port 1.2/adc2 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .3?.2 port 1.1/adc1 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .1?.0 port 1.0/adc0 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain
s3c852b/P852B (p reliminary s pec ) control registers 4- 25 p2con ? port 2 control register efh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 port 2.3 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .5? .4 port 2.2 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .3?2 port 2.1 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .1? .0 port 2.0 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain
control registers s 3c852b/P852B (p reliminary s pec ) 4- 26 p3afs ? port 3 function select register f2h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 not used for s3c852b/P852B .3 port 3.3/ wr wr 0 normal i/o port 1 select alternative function for wr .2 port 3.2/ rd rd 0 normal i/o port 1 select alternative function for rd .1 port 3.1/ dm dm 0 normal i/o port 1 select alternative function for dm .0 port 3.0/ pm pm 0 normal i/o port 1 select alternative function for pm
s3c852b/P852B (p reliminary s pec ) control registers 4- 27 p3con ? port 3 control register f1h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 port 3.3/ wr wr 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .5?.4 port 3.2/ rd rd 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .3?.2 port 3.1/ dm dm 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .1?.0 port 3.0/ pm pm 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain
control registers s 3c852b/P852B (p reliminary s pec ) 4- 28 p4con ? port 4 control register f3h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 port 4.7?port 4.4/d7?d4 0 0 0 0 input, schmitt trigger 0 0 0 1 input, schmitt trigger, pull-up resistor 0 0 1 0 output, push-pull 0 0 1 1 output, open-drain 0 1 0 0 select external memory interface line at d7?d4 .3?.0 port 4.3?port 4.0/d3?d0 0 0 0 0 input, schmitt trigger 0 0 0 1 input, schmitt trigger, pull-up resistor 0 0 1 0 output, push-pull 0 0 1 1 output, open-drain 0 1 0 0 select external memory interface line at d3?d0
s3c852b/P852B (p reliminary s pec ) control registers 4- 29 p5con ? port 5 control register f4h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 port 5.7?port 5.4/a7?a4 0 0 0 0 input, schmitt trigger 0 0 0 1 input, schmitt trigger, pull-up resistor 0 0 1 0 output, push-pull 0 0 1 1 output, open-drain 0 1 0 0 select external memory interface line at a7?a4 .3?.0 port 5.3?port 5.0/a3?a0 0 0 0 0 input, schmitt trigger 0 0 0 1 input, schmitt trigger, pull-up resistor 0 0 1 0 output, push-pull 0 0 1 1 output, open-drain 0 1 0 0 select external memory interface line at a3?a0
control registers s 3c852b/P852B (p reliminary s pec ) 4- 30 p6con ? port 6 control register f5h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?4 port 6.7?port 6.4/a15?a12 0 0 0 0 input, schmitt trigger 0 0 0 1 input, schmitt trigger, pull-up resistor 0 0 1 0 output, push-pull 0 0 1 1 output, open-drain 0 1 0 0 select external memory interface line at a15?a12 .3?0 port 6.3?port 6.0/a11?a8 0 0 0 0 input, schmitt trigger 0 0 0 1 input, schmitt trigger, pull-up resistor 0 0 1 0 output, push-pull 0 0 1 1 output, open-drain 0 1 0 0 select external memory interface line at a11?a8
s3c852b/P852B (p reliminary s pec ) control registers 4- 31 p7conh ? port 7 control register(high byte) f8h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 port 7.7 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .5?.4 port 7.6 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .3?.2 port 7.5 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .1?.0 port 7.4 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain
control registers s 3c852b/P852B (p reliminary s pec ) 4- 32 p7conl ? port 7 control register(low byte) f9h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 port 7.3 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .5?.4 port 7.2 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .3?.2 port 7.1 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .1?.0 port 7.0 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain
s3c852b/P852B (p reliminary s pec ) control registers 4- 33 p8conh ? port 8 control register(high byte) fah set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 port 8.7 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .5?.4 port 8.6 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .3?.2 port 8.5 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .1?.0 port 8.4 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain
control registers s 3c852b/P852B (p reliminary s pec ) 4- 34 p8conl ? port 8 control register(low byte) fbh set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 port 8.3 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .5?.4 port 8.2 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .3?.2 port 8.1 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .1?.0 port 8.0 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain
s3c852b/P852B (p reliminary s pec ) control registers 4- 35 p9conh ? port 9 control register(high byte) fch set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 port 9.7 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .5?.4 port 9.6 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .3?.2 port 9.5 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .1?.0 port 9.4 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain
control registers s 3c852b/P852B (p reliminary s pec ) 4- 36 p9conl ? port 9 control register(low byte) fdh set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 port 9.3 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .5?.4 port 9.2 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .3?.2 port 9.1 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .1?.0 port 9.0 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain
s3c852b/P852B (p reliminary s pec ) control registers 4- 37 p10conh ? port 10 control register(high byte) feh set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 port 10.7 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .5?.4 port 10.6 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .3?.2 port 10.5 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .1?.0 port 10.4 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain
control registers s 3c852b/P852B (p reliminary s pec ) 4- 38 p10conl ? port 10 control register(low byte) ffh set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 port 10.3 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .5?.4 port 10.2 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .3?.2 port 10.1 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain .1?.0 port 10.0 0 0 input, schmitt trigger 0 1 input, schmitt trigger, pull-up resistor 1 0 output, push-pull 1 1 output, open-drain
s3c852b/P852B (p reliminary s pec ) control registers 4- 39 pp ? register page pointer dfh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 destination register page selection bits 0 0 0 0 destination: page 0 0 0 0 1 destination: page 1 0 0 1 0 destination: page 2 0 0 1 1 destination: page 3 0 1 0 0 destination: page 4 1 1 1 1 destination: page f .3?.0 source register page selection bit 0 0 0 0 source: page 0 0 0 0 1 source: page 1 0 0 1 0 source: page 2 0 0 1 1 source: page 3 0 1 0 0 source: page 4 1 1 1 1 source: page f
control registers s 3c852b/P852B (p reliminary s pec ) 4- 40 rp0 ? register pointer 0 d6h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 1 0 0 0 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? addressing mode register addressing only .7?.3 register pointer 0 address value register pointer 0 can independently point to one of the 24 8-byte working register areas in the register file. using the register pointers rp0 and rp1, you can select two 8-byte register slices at one time as active working register space. after a reset, rp0 points to address c0h in register set 1, selecting the 8-byte working register slice c0h?c7h. .2?.0 not used for s3c852b/P852B rp1 ? register pointer 1 d7h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 1 0 0 1 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? addressing mode register addressing only .7?.3 register pointer 1 address value register pointer 1 can independently point to one of the 24 8-byte working register areas in the register file. using the register pointers rp0 and rp1, you can select two 8-byte register slices at one time as active working register space. after a reset, rp1 points to address c8h in register set 1, selecting the 8-byte working register slice c8h?cfh. .2?.0 not used for s3c852b/P852B
s3c852b/P852B (p reliminary s pec ) control registers 4- 41 siocon ? sio control register ebh set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 sio shift clock selection bit 0 internal clock (p.s clock) 1 external clock (sck) .6 data direction control bit 0 msb first mode 1 lsb first mode .5 sio mode selection bit 0 receive only mode 1 transmit/receive mode .4 shift start edge selection bit 0 tx at falling edges, rx at rising edges 1 tx at rising edges, rx at falling edges .3 sio counter clear and shift start bit 0 no action 1 clear 3-bit counter and start shifting .2 sio shift operation enable bit 0 disable shifter and clock counter 1 enable shifter and clock counter .1 sio interrupt enable bit 0 disable sio interrupt 1 enable sio interrupt .0 sio interrupt pending bit 0 no interrupt pending 0 clear pending condition (when write) 1 interrupt is pending
control registers s 3c852b/P852B (p reliminary s pec ) 4- 42 siops ? sio prescaler register ech set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 baud rate = input clock (fxx)/[(siops + 1) 4] or sclk input clock
s3c852b/P852B (p reliminary s pec ) control registers 4- 43 sph ? stack pointer (high byte) d8h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 stack pointer address (high byte) the high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (sp15?sp8). the lower byte of the stack pointer value is located in register spl (d9h). the sp value is undefined following a reset. note: if you only use the internal register file as stack area, sph can serve as a general-purpose register. to avoid possible overflows or under flows of the spl register by operations that increment or decrement the stack, we recommend that you initialize spl with the value 'ffh' instead of '00h'. if you use external me mory as stack area, the stack pointer requires a full 16-bit address. spl ? stack pointer (low byte) d9h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 stack pointer address (low byte) the low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer address (sp7?sp0). the upper byte of the stack pointer value is located in register sph (d8h). the sp value is undefined following a reset.
control registers s 3c852b/P852B (p reliminary s pec ) 4- 44 stpcon ? stop control register fbh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 stop control bits 00000000 disable stop instruction 10100101 enable stop instruction
s3c852b/P852B (p reliminary s pec ) control registers 4- 45 sym ? system mode register deh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 ? ? x x x 0 0 read/write r/w ? ? r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 tri-state external interface control bit 0 normal operation (disable tri-state operation) 1 set external interface lines to high impedance (enable tri-state operation) .6 and .5 not used for s3c852b/P852B .4?.2 fast interrupt level selection bits 0 0 0 irq0 (timer 0 overflow/match and capture) 0 0 1 irq1 (timer a match, timer b overflow/match) 0 1 0 irq2 (caller id functions) 0 1 1 irq3 (watch timer overflow) 1 0 0 irq4 (serial data receive/transmit interrupt) 1 0 1 not used for s3c852b/P852B 1 1 0 irq6 (int0?int3) 1 1 1 irq7 (int4?int7) .1 fast interrupt enable bit 0 disable fast interrupt processing 1 enable fast interrupt processing .0 global interrupt enable bit (note) 0 disable global interrupt processing 1 enable global interrupt processing note : following a reset, you enable global interrupt processing by executing an ei instruction (not by writing a "1" to sym.0).
control registers s 3c852b/P852B (p reliminary s pec ) 4- 46 t0con ? timer a control register d2h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 timer 0 input clock selection bits 0 0 fxx/1024 0 1 fxx/256 1 0 fxx/64 1 1 external clock (p0.2/t0ck) .5 - .4 timer 0 operating mode selection bits 0 0 interval mode (p0.3/t0) 0 1 capture mode (capture on rising edge, counter running, ovf can occur) 1 0 capture mode (capture on falling edge, counter running, ovf can occur) 1 1 pwm mode (ovf interrupt can occur) .3 timer 0 counter clear bit 0 no effect 1 clear the timer 0 counter (when write) .2 timer 0 overflow interrupt enable bit 0 disable interrupt 1 enable interrupt .1 timer 0 match/capture interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer 0 match/capture interrupt pending bit 0 no interrupt pending 0 clear pending bit (write) 1 interrupt is pending
s3c852b/P852B (p reliminary s pec ) control registers 4- 47 tacon ? timer a control register e4h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 one 16-bit timer or two 8-bit timers mode selection bit 0 two 8-bit timers mode (timer a/timer b) 1 one 16-bit timer mode (timer 1) .6?.4 timer a clock selection bits 0 0 0 fxx/1024 0 0 1 fxx/512 0 1 0 fxx/8 0 1 1 fxx 1 x x t1ck (external clock) (?x? means don?t care.) .3 timer a counter clear bit 0 no effect 1 clear the timer a counter (when write) .2 timer a count enable bit 0 disable count operation 1 enable count operation .1 timer a interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer a interrupt pending bit 0 no interrupt pending 0 clear pending bit (when write) 1 interrupt is pending
control registers s 3c852b/P852B (p reliminary s pec ) 4- 48 tbcon ? timer b control register e5h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 timer b operating mode selection bits 0 0 interval mode 0 1 6-bit pwm mode (ovf interrupt can occur) 1 0 7-bit pwm mode (ovf interrupt can occur) 1 1 8-bit pwm mode (ovf interrupt can occur) .5?.4 timer b clock selection bits 0 0 fxx/8 0 1 fxx/4 1 0 fxx/2 1 1 fxx .3 timer b counter clear bit 0 no effect 1 clear the timer b counter (when write) .2 timer b count enable bit 0 disable count operation 1 enable count operation .1 timer b match interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer b overflow interrupt enable bit 0 disable interrupt 1 enable interrupt
s3c852b/P852B (p reliminary s pec ) control registers 4- 49 wtcon ? watch timer control register e6h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 watch timer clock selection bit 0 main clock divide by 2 7 (fx/128) 1 sub clock (fxt) .6 watch timer int enable/disable bit 0 disable watch timer interrupt 1 enable watch timer interrupt .5?.4 buzzer signal selection bits 0 0 2 khz 0 1 4 khz 1 0 8 khz 1 1 16 khz .3?.2 watch timer speed selection bits 0 0 set watch timer interrupt to 1 s 0 1 set watch timer interrupt to 0.5 s 1 0 set watch timer interrupt to 0.25 s 1 1 set watch timer interrupt to 3.91ms note: the above values of watch timer interrupt are accurate when fw = fxt. .1 watch timer enable/disable bit 0 disable watch timer; clear frequency dividing circuits 1 enable watch timer .0 watch timer interrupt pending bit 0 watch timer interrupt request is not pending 1 watch timer interrupt request is pending
control registers s 3c852b/P852B (p reliminary s pec ) 4- 50 notes
s3c852b/P852B (preliminary spec) interrupt structur e 5- 1 5 interrupt structure overview the sam8 interrupt structure has three basic components: levels, vectors, and sources. the cpu recognizes eight interrupt levels and supports up to 128 interrupt vectors. when a specific interrupt level has more than one vector address, the vector priorities are established in hardware. each vector can have one or more sources. levels interrupt levels are the main unit for interrupt priority assignment and recognition. all peripherals and i/o blocks can issue interrupt requests. in other words, peripheral and i/o operations are interrupt-driven. there are eight interrupt levels: irq0?irq7, also called level 0-level 7. each interrupt level directly corresponds to an interrupt request number (irqn). the total number of interrupt levels used in the interrupt structure varies from device to device. the s3c852b/P852B interrupt structure recognizes eight interrupt levels, irq0?irq7. the interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. they are simply identifiers for the interrupt levels that are recognized by the cpu. the relative priority of different interrupt levels is determined by settings in the interrupt priority register, ipr. interrupt group and subgroup logic controlled by ipr settings lets you define more complex priority relationships between different levels. vectors each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. the maximum number of vectors that can be supported for a given level is 128. (the actual number of vectors used for tcc12x-series devices will always be much smaller.) if an interrupt level has more than one vector address, the vector priorities are set in hardware. s3c852b/P852B have eighteen vectors? corresponding to each of the eighteen possible interrupt sources. sources a source is any peripheral that generates an interrupt. a source can be an external pin or a counter overflow, for example. each vector can have several interrupt sources. in the s3c852b/P852B interrupt structure, each source has its own vector address. when a service routine starts, the respective pending bit is either cleared automatically by hardware cleared "manually" by program software. the characteristics of the source's pending mechanism determine which method is used to clear its respective pending bit.
interrupt structure s3c852b/P852B (preliminary spec) 5- 2 interrupt types the three components of the sam8 interrupt structure described above ( levels, vectors, and sources ) are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. there are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3. the types differ in the number of vectors and interrupt sources assigned to each level (see figure 5-1): type 1: one level (irqn) + one vector (v 1 ) + one source (s 1 ) type 2: one level (irqn) + one vector (v 1 ) + multiple sources (s 1 ?s n ) type 3: one level (irqn) + multiple vectors (v 1 ?v n ) + multiple sources (s 1 ?s n , s n+1? s n+m ) in the s3c852b/P852B microcontrollers, only interrupt types 1 and 3 are implemented. vectors sources levels s 1 v 1 s 2 type 2: irqn s 3 s n v 1 s 1 v 2 s 2 type 3: irqn v 3 s 3 v 1 s 1 type 1: irqn v n s n + 1 s n s n + 2 s n + m notes: 1. the number of s n and v n value is expandable. 2. in the s3c852b/P852B implementation, only interrupt types 1 and 3 are used. figure 5-1. sam8-series interrupt types
s3c852b/P852B (preliminary spec) interrupt structur e 5- 3 s3c852b/P852B interrupt structure the s3c852b/P852B microcontroller supports eighteen interrupt sources. each interrupt source has a corresponding interrupt vector address. seventh interrupt levels are used in the device-specific interrupt structure, which is shown in figure 5-2. when multiple interrupt levels are active, the interrupt priority register (ipr) determines the order in which contending interrupts are to be serviced. if multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first. when the cpu grants an interrupt request, interrupt processing starts: all other interrupts are disabled and the program counter value and status flags are pushed to stack. the starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed. vectors sources levels reset/clear irq1 f6h timer b overflow f4h timer a match timer 0 overflow fah timer b match f8h irq0 watch timer oveflow f2h serial data reveive/transmit f0h irq3 irq4 p0.3 external interrupt p0.2 external interrupt p0.1 external interrupt p0.0 external interrupt irq6 d6h d4h d2h d0h p0.7 external interrupt p0.6 external interrupt p0.5 external interrupt p0.4 external interrupt irq7 eah e8h e6h e4h basic timer overflow reset fch timer 0 match & capture 100h h/w h/w s/w s/w h/w s/w s/w s/w s/w s/w s/w s/w s/w s/w s/w s/w 0 2 1 0 0 1 0 3 2 0 3 1 1 2 0 cid interrupt d8h irq2 0 s/w figure 5-2. s3c852b interrupt structure
interrupt structure s3c852b/P852B (preliminary spec) 5- 4 interrupt vector addresses interrupt vector addresses for the s3c852b/P852B are stored in the first 256 bytes of the program memory (rom). vectors for all interrupt levels are stored in the vector address area, 0h?ffh. unused locations in this range can be used as normal program memory. when writing an application program, you should be careful not to overwrite the address data stored in this area. the program reset address in the program memory is 0100h. 65,535 0 (decimal) 255 00h 0100h ffh ffffh (hex) reset address interrupt vector area 64-kbyte memory area ~ ~ ~ ~ figure 5-3. vector address area in program memory (rom)
s3c852b/P852B (preliminary spec) interrupt structur e 5- 5 table 5-1. s3c852b/P852B interrupt vectors vector address interrupt source request reset/clear decimal value hex value interrupt level priority in level h/w s/w 208 d0h p0.0 external interrupt(edge trigger) irq6 0 ? 210 d2h p0.1 external interrupt(edge trigger) 1 212 d4h p0.2 external interrupt(edge trigger) 2 214 d6h p0.3 external interrupt(edge trigger) 3 216 d8h cid interrupt irq2 2 ? 228 e4h p0.4 external interrupt(edge trigger) irq7 0 ? 230 e6h p0.5 external interrupt(edge trigger) 1 232 e8h p0.6 external interrupt(edge trigger) 2 234 eah p0.7 external interrupt(edge trigger) 3 240 f0h serial data receive/transmit irq4 - ? 242 f2h watch timer overflow irq3 - ? 244 f4h timer a match irq1 0 ? 246 f6h timer b overflow 1 ? 248 f8h timer b match 2 ? 250 fah timer 0 overflow irq0 0 ? 252 fch timer 0 match & capture 1 ? 256 100h basic timer overflow - - ? notes: 1. interrupt priorities are identified in inverse order: '0' is highest priority, '1' is the next highest, and so on. 2. if two or more interrupts within the same level contend, the interrupt with the lowest vector address has priority over one with a higher vector address. these priorities within levels are preset at the factory.
interrupt structure s3c852b/P852B (preliminary spec) 5- 6 enable/disable interrupt instructions (ei, di) executing the enable interrupts (ei) instruction enables the interrupt structure. all interrupts are then serviced as they occur, and according to the established priorities. note the system initialization routine that is executed following a reset must always contain an ei instruction (assuming one or more interrupts are used in the application). during normal operation, you can execute the di (disable interrupt) instruction at any time to globally disable interrupt processing. the ei and di instructions change the value of bit 0 in the sym register. although you can manipulate sym.0 directly to enable or disable interrupts, we recommend that you use the ei and di instructions instead. system-level interrupt control registers in addition to the control registers for specific interrupt sources, four system-level registers control interrupt processing: ? the interrupt mask register, imr, enables (un-masks) or disables (masks) interrupt levels. ? the interrupt prior ity register, ipr, controls the relative priorities of interrupt levels. ? the interrupt request register, irq, contains interrupt pending flags for each interrupt level (as opposed to each interrupt source). ? the system mode register, sym, enables or disables global interrupt processing. (sym settings also enable fast interrupts and control the activity of external interface, if implemented.) table 5-2. interrupt control register overview control register id r/w function description interrupt mask register imr r/w bit settings in the imr register enable or disable interrupt processing for each of the seven interrupt levels, irq0?irq7. interrupt priority register ipr r/w controls the relative processing priorities of the interrupt levels. the eight levels of the s3c852b/P852B are organized into three groups: a, b, and c. group a is irq0 and irq1, group b is irq2?irq4, and group c is irq6?irq7 interrupt request register irq r this register contains a request pending bit for each of the seven interrupt levels, irq0?rq7. system mode register sym r/w dynamic global interrupt processing enable and disable, fast interrupt processing. note di instruction must be used before changing the imr, interrupt pending register and interrupt source control register. if imr, interrupt pending register or source control register is controlled in ei status, program control could be in uncontrollable state.
s3c852b/P852B (preliminary spec) interrupt structur e 5- 7 interrupt processing control points interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. the system-level control points in the interrupt structure are, therefore: ? global interrupt enable and disable (by ei and di instructions or by direct manipulation of sym.0 ) ? interrupt level enable/disable settings (imr register) ? interrupt level priority settings (ipr register) ? interrupt source enable/disable settings in the corresponding peripheral control r egisters note when writing the part of your application program that handles interrupt processing, be sure to include the necessary register file address (register pointer) information. interrupt request register (read-only) interrup pending (read-only) interrupt mask register interrupt priority register global interrupt control (ei, di or sym.0 manipulation) s r q reset ei instruction execution vector interrupt cycle source interrupt enable figure 5-4. interrupt function diagram
interrupt structure s3c852b/P852B (preliminary spec) 5- 8 system mode register (sym) the system mode register, sym (set 1, deh), is used to globally enable and disable interrupt processing and to control fast interrupt processing. figure 5-5 shows the effect of the various control settings. a reset clears sym.7, sym.1, and sym.0 to "0" and the other sym bit values (for fast interrupt level selection) are undetermined. the instructions ei and di enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the sym register. an enable interrupt (ei) instruction must be included in the initialization routine, which follows a reset operation, in order to enable interrupt processing. although you can manipulate sym.0 directly to enable and disable interrupts during normal operation, we recommend using the ei and di instructions for this purpose. system mode register (sym) deh, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb global interrupt enable bit: 0 = disable all interrupts 1 = enable all interrupts fast interrupt enable bit: 0 = disable fast interrupts 1 = enable fast interrupts fast interrupt level selection bits: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 irq0 irq1 irq2 irq3 irq4 not used for s3c852b/P852B irq6 irq7 not used external interface tri-state enable bit: 0 = normal operation (tri-state disable) 0 = high inpedence (tri-state enable) figure 5-5. system mode register (sym)
s3c852b/P852B (preliminary spec) interrupt structur e 5- 9 interrupt mask register (imr) the interrupt mask register, imr (set 1, ddh) is used to enable or disable interrupt processing for individual interrupt levels. after a reset, all imr bit values are undetermined and must therefore be written to their required settings by the initialization routine. each imr bit corresponds to a specific interrupt level: bit 1 to irq1, bit 2 to irq2, and so on. when the imr bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). when you set a level's imr bit to "1", interrupt processing for the level is enabled (not masked). the imr register is mapped to register location ddh in set 1. bit values can be read and written by instructions using the register addressing mode. interrupt mask register (imr) ddh, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb irq1 irq2 irq4 not used for s3c852b/P852B irq6 irq7 irq0 interrupt level enable bits 0 = disable (mask) interrupt level 1 = enable (un-mask) interrupt level irq3 figure 5-6. interrupt mask register (imr) note before imr register is changed to any value, all interrupts must be disable. using di instruction is recommended.
interrupt structure s3c852b/P852B (preliminary spec) 5- 10 interrupt priority register (ipr) the interrupt priority register, ipr (set 1, bank 0, ffh), is used to set the relative priorities of the interrupt levels used in the microcontroller?s interrupt structure. after a reset, all ipr bit values are undetermined and must therefore be written to their required settings by the initialization routine. when more than one interrupt source is active, the source with the highest priority level is serviced first. if both sources belong to the same interrupt level, the source with the lowest vector address usually has priority. (this priority is fixed in hardware.) to support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. please note that these groups (and subgroups) are used only by ipr logic for the ipr register priority definitions (see figure 5-7): group a irq0, irq1 group b irq2, irq3, irq4 group c irq6, irq7 ipr group b ipr group c c2 irq7 irq2 b1 irq4 b2 irq3 b22 b21 ipr group a irq1 a2 irq0 a1 irq6 c1 figure 5-7. interrupt request priority groups as you can see in figure 5-8, ipr.7, ipr.4, and ipr.1 control the relative priority of interrupt groups a, b, and c. for example, the setting '001b' for these bits would select the group relationship b > c > a; the setting '101b' would select the relationship c > b > a. the functions of the other ipr bit settings are as follows: ? ipr.6 controls the relative priorities of group c interrupts. ? interrupt group b has a subgroup to provide an additional priority relationship between for interrupt levels 2, 3, and 4. ipr.2 defines the possible subgroup b relationships. ? ipr.3 controls the relative priorities setting of irq3 and irq4 interrupts. ? ipr.0 controls the relative priority setting of irq0 and irq1 interrupts.
s3c852b/P852B (preliminary spec) interrupt structur e 5- 11 interrupt priority register (ipr) ffh, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb group a 0 = irq0 > irq1 1 = irq1 > irq0 subgroup b 0 = irq3 > irq4 1 = irq4 > irq3 group c 0 = irq6 > irq7 1 = irq7 > irq6 subgroup c 0 = irq6 > irq7 1 = irq7 > irq6 group b 0 = irq2 > (irq3,irq4) 1 = (irq3,irq4) > irq2 group priority: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 = undefined = b > c > a = a > b > c = b > a > c = c > a > b = c > b > a = a > c > b = not used d7 d4 d1 figure 5-8. interrupt priority register (ipr)
interrupt structure s3c852b/P852B (preliminary spec) 5- 12 interrupt request register (irq) you can poll bit values in the interrupt request register, irq (set 1, dch), to monitor interrupt request status for all levels in the microcontroller? interrupt structure. each bit corresponds to the interrupt level of the same number: bit 0 to irq0, bit 1 to irq1, and so on. a "0" indicates that no interrupt request is currently being issued for that level; a "1" indicates that an interrupt request has been generated for that level. irq bit values are read-only addressable using register addressing mode. you can read (test) the contents of the irq register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. after a reset, all irq status bits are cleared to "0". you can poll irq register values even if a di instruction has been executed (that is, if global interrupt processing is disabled). if an interrupt occurs while the interrupt structure is disabled, the cpu will not service it. you can, however, still detect the interrupt request by polling the irq register. in this way, you can determine which events occurred while the interrupt structure was globally disabled. interrupt request register (irq) dch, set 1, read-only .7 .6 .5 .4 .3 .2 .1 .0 msb lsb irq1 irq2 irq3 irq4 not used for s3c852b/P852B irq6 irq7 irq0 interrupt level request pending bits: 0 = interrupt level is not pending 1 = interrupt level is pending figure 5-9. interrupt request register (irq)
s3c852b/P852B (preliminary spec) interrupt structur e 5- 13 interrupt pending function types overview there are two types of interrupt pending bits: one type is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other type must be cleared by the application program's interrupt service routine. pending bits cleared automatically by hardware for interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. it then issues an irq pulse to inform the cpu that an interrupt is waiting to be serviced. the cpu acknowledges the interrupt source, executes the service routine, and clears the pending bit to "0". this type of pending bit is mapped and can, therefore, be read or written by application software. please refer to the page 5-4 (interrupt structure) to recognize which interrupts belong to this category of interrupts whose pending conditions are cleared automatically by hardware. pending bits cleared by the service routine the second type of pending bit must be cleared by program software. the service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (iret) occurs. to do this, a "0" must be written to the corresponding pending bit location in the source or control register. in the s3c852b/P852B interrupt structure, pending conditions for all external interrupt sources must be cleared by the program software's interrupt service routine.
interrupt structure s3c852b/P852B (preliminary spec) 5- 14 interrupt source polling sequence the interrupt request polling and servicing sequence is as follows: 1. a source generates an interrupt request by setting the interrupt request bit to "1". 2. the cpu polling procedure identifies a pending condition for that source. 3. the cpu checks the source's interrupt level. 4. the cpu generates an interrupt acknowledge signal. 5. interrupt logic determines the interrupt's vector address. 6. the service routine starts and the source's pending bit is cleared to "0" (by hardware or by software). 7. the cpu continues polling for interrupt requests. interrupt service routines before an interrupt request can be serviced, the following conditions must be met: ? interrupt processing must be globally enabled (ei, sym.0 = "1") ? the interrupt level must be enabled (imr register) ? the interrupt level must have the highest priority if more than one level is currently requesting service ? the interrupt must be enabled at the interrupt's source (peripheral control register) if all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the interrupt enable bit in the sym register (sym.0) to disable all subsequent interrupts. 2. save the program counter (pc) and stat us flags to the system stack. 3. branch to the interrupt vector to fetch the address of the service routine'. 4. pass control to the interrupt service routine. when the interrupt service routine is completed, the cpu issues an interrupt return (iret). the iret restores the pc and status flags and sets sym.0 to "1", allowing the cpu to process the next interrupt request.
s3c852b/P852B (preliminary spec) interrupt structur e 5- 15 generating interrupt vector addresses the interrupt vector area in the rom (00h?ffh) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to the stack. 2. push the program counter's high-byte value to the stack. 3. push the flag register values to the stack. 4. fetch the service routine's high-byte address from the vector location. 5. fetch the service routine's low-byte address from the vector location. 6. branch to the service routine s pecified by the concatenated 16-bit vector address. note a 16-bit vector address always begins at an even-numbered rom address within the range 00h - ffh. nesting of vectored interrupts it is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. to do this, you must follow these steps: 1. push the current 8-bit interrupt mask register (imr) value to the stack (push imr). 2. load the imr register with a new mask val ue that enables only the higher priority interrupt. 3. execute an ei instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs). 4. when the lower-priority interrupt service routine ends, execute di, and restore the imr to its original value by returning the previous mask value from the stack (pop imr). 5. execute an iret. depending on the application, you may be able to simplify the above procedure to some extent. instruction pointer (ip) the instruction pointer (ip) is used by all ks88-series microcontrollers to control the optional high-speed interrupt processing feature called fast interrupts . the ip consists of register pair dah and dbh. the ip register names are iph (high byte, ip15?ip8) and ipl (low byte, ip7?ip0).
interrupt structure s3c852b/P852B (preliminary spec) 5- 16 fast interrupt processing the feature called fast interrupt processing lets you specify that an interrupt within a given level be completed in approximately six clock cycles instead of the usual 16 clock cycles. sym.4?sym.2 are used to select a specific interrupt level for fast processing and sym.1 enables or disables fast interrupt processing. two other system registers support fast interrupt processing: ? the instruction pointer (ip) contains the starting address of the service routine (and is later used to swap the program counter values), and ? when a fast interrupt occurs, the contents of the flags register is stored in an unmapped, dedicated register called flags' (flags prime). notes 1. for the s3c852b/P852B microcontroller?s, the service routine for any of the seven interrupt levels can be selected for fast interrupt processing. 2. if you want to use a fast interrupt in multi source interrupt vector, the fast interrupt may not be processed when you use two sources as interrupt vector in normal mode. but it is possible when you use only one source as interrupt vector. procedure for initiating fast interrupts to initiate fast interrupt processing, follow these steps: 1. load the start address of the service routine into the instruction pointer (ip). 2. load the interrupt level number (irqn) into the fast interrupt selection field (sym.4?sym.2) 3. write a "1" to the fast interrupt enable bit in the sym register. fast interrupt service routine when an interrupt occurs in the level selected for fast interrupt processing, the following events occur: 1. the contents of the instruction pointer and the pc are swapped. 2. the flag register values are written to the flags' (?flags prime?) register. 3. the fast interrupt status bit in the flags register is set. 4. the interrupt is serviced. 5. assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction pointer and pc values are swapped back. 6. the content of flags' (?flags prime?) is copied automatically back to the flags register. 7. the fast interrupt status bit in flags is cleared automatically.
s3c852b/P852B (preliminary spec) interrupt structur e 5- 17 relationship to interrupt pending bit types as described previously, there are two types of interrupt pending bits: one type is automatically cleared by hardware after the interrupt service routine is acknowledged and executed, and the other type must be cleared by the application program's interrupt service routine. you can select fast interrupt processing for interrupts with either type of pending condition clear function ? by hardware or by software. programming guidelines remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the sym register, sym.1. executing an ei or di instruction globally enables or disables all interrupt processing, including fast interrupts. note if you use fast interrupts, remember to load the ip with a new start address when the fast interrupt service routine ends.
interrupt structure s3c852b/P852B (preliminary spec) 5- 18 f f programming tip ? setting up the s3c852b interrupt control structure this example shows how to enable interrupts for select interrupt sources, disable interrupt for other sources, and to set interrupt priorities for the s3c852b. the program does the following: ? enable interrupts for timer 0, serial, and external interrupt(int4 ? int7) ? set interrupt priorities as sio > timer 0 > external interrupt(int4 ? int7) ? ? ? di ; disable interrupts ld imr,#91h ; irq0, irq4, irq7 are selected ld ipr,#12h ; irq4 > irq0 > irq7 ld t0data,#0ffh ; ld t0con,#12h ; timer 0 interrupt enable, timer 0 pending clear sb1 ld siocon,#3 eh ; sio interrupt enable ld siops,#29h ; sio prescaler setting ld p0int, #0f0h ; external interrupt(int4 ? int7) enable ? ? ? ei ; enable interrupts assuming interrupt sources and priorities have been set by the above instruction sequence, you could then select interrupt level 0, 2, or 7 for fast interrupt processing. the following instructions enable fast interrupt processing for irq7: di ; disable interrupts ldw iph,#3000h ; load the service routine address for irq7 ld sym,#1eh ; enable fas t interrupt processing ei ; enable interrupts
s3c852b/P852B (preliminary spec) instruction set 6- 1 6 instruction set overview the sam87rc instruction set is specifically designed to support the large register files that are typical of most sam87rc microcontrollers. there are 78 instructions. the powerful data manipulation capabilities and features of the instruction set include: ? a full complement of 8-bit arithmetic and logic operations, including multiply and divide ? no special i/o instructions (i/o control/data registers are mapped directly into the register file) ? decimal adjustment included in binary-coded decimal (bcd) operations ? 16-bit (word) data can be incremented and decremented ? flexible instructions for bit addressing, rotate, and shift operations data types the sam87rc cpu performs operations on bits, bytes, bcd digits, and two-byte words. bits in the register file can be set, cleared, complemented, and tested. bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit. register addressing to access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. paired registers can be used to construct 16-bit data or 16-bit program memory or data memory addresses. for detailed information about register addressing, please refer to section 2, "address spaces." addressing modes there are seven explicit addressing modes: register (r), indirect register (ir), indexed (x), direct (da), relative (ra), immediate (im), and indirect (ia). for detailed descriptions of these addressing modes, please refer to section 3, "addressing modes."
instruction set s3c 852b/P852B (preliminary spec) 6- 2 table 6-1. instruction group summary mnemonic operands instruction load instructions clr dst clear ld dst, src load ldb dst, src load bit lde dst, src load external data memory ldc dst, src load program memory lded dst, src load external data memory and decrement ldcd dst, src load program memory and decrement ldei dst, src load external data memory and increment ldci dst, src load program memory and increment ldepd dst, src load external data memory with pre-decrement ldcpd dst, src load program memory with pre-decrement ldepi dst, src load external data memory with pre-increment ldcpi dst, src load program memory with pre-increment ldw dst, src load word pop dst pop from stack popud dst, src pop user stack (decrementing) popui dst, src pop user stack (incrementing) push src push to stack pushud dst, src push user stack (decrementing) pushui dst, src push user stack (incrementing)
s3c852b/P852B (preliminary spec) instruction set 6- 3 table 6-1. instruction group summary (continued) mnemonic operands instruction arithmetic instructions adc dst, src add with carry add dst, src add cp dst, src compare da dst decimal adjust dec dst decrement decw dst decrement word div dst, src divide inc dst increment incw dst increment word mult dst, src multiply sbc dst, src subtract with carry sub dst, src subtract logic instructions and dst, src logical and com dst complement or dst, src logical or xor dst, src logical exclusive or
instruction set s3c 852b/P852B (preliminary spec) 6- 4 table 6-1. instruction group summary (continued) mnemonic operands instruction program control instructions btjrf dst, src bit test and jump relative on false btjrt dst, src bit test and jump relative on true call dst call procedure cpije dst, src compare, increment and jump on equal cpijne dst, src compare, increment and jump on non-equal djnz r, dst decrement register and jump on non-zero enter enter exit exit iret interrupt return jp cc dst jump on condition code jp dst jump unconditional jr cc dst jump relative on condition code next next ret return wfi wait for interrupt bit manipulation instructions band dst, src bit and bcp dst, src bit compare bitc dst bit complement bitr dst bit reset bits dst bit set bor dst, src bit or bxor dst, src bit xor tcm dst, src test complement under mask tm dst, src test under mask
s3c852b/P852B (preliminary spec) instruction set 6- 5 table 6-1. instruction group summary (concluded) mnemonic operands instruction rotate and shift instructions rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic swap dst swap nibbles cpu control instructions ccf complement carry flag di disable interrupts ei enable interrupts idle enter idle mode nop no operation rcf reset carry flag sb0 set bank 0 sb1 set bank 1 scf set carry flag srp src set register pointers srp0 src set register pointer 0 srp1 src set register pointer 1 stop enter stop mode
instruction set s3c 852b/P852B (preliminary spec) 6- 6 flags register (flags) the flags register flags contains eight bits that describe the current status of cpu operations. four of these bits, flags.7?flags.4, can be tested and used with conditional jump instructions; two others flags.3 and flags.2 are used for bcd arithmetic. the flags register also contains a bit to indicate the status of fast interrupt processing (flags.1) and a bank address status bit (flags.0) to indicate whether bank 0 or bank 1 is currently being addressed. flags register can be set or reset by instructions as long as its outcome does not affect the flags, such as, load instruction. logical and arithmetic instructions such as, and, or, xor, add, and sub can affect the flags register. for example, the and instruction updates the zero, sign and overflow flags based on the outcome of the and instruction. if the and instruction uses the flags register as the destination, then simultaneously, two write will occur to the flags register producing an unpredictable result. system flags register (flags) d5h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb bank address status flag (ba) fast interrupt status flag (fs) half-carry flag (h) decimal adjust flag (d) carry flag (c) zero flag (z) sign flag (s) overflow flag (v) figure 6-1. system flags register (flags)
s3c852b/P852B (preliminary spec) instruction set 6- 7 flag descriptions c carry flag (flags.7) the c flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (msb). after rotate and shift operations, it contains the last value shifted out of the specified register. program instructions can set, clear, or complement the carry flag. z zero flag (flags.6) for arithmetic and logic operations, the z flag is set to "1" if the result of the operation is zero. for operations that test register bits, and for shift and rotate operations, the z flag is set to "1" if the result is logic zero. s sign flag (flags.5) following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the msb of the result. a logic zero indicates a positive number and a logic one indicates a negative number. v overflow flag (flags.4) the v flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than ? 128. it is also cleared to "0" following logic operations. d decimal adjust flag (flags.3) the da bit is used to specify what type of instruction was executed last during bcd operations, so that a subsequent decimal adjust operation can execute correctly. the da bit is not usually accessed by programmers, and cannot be used as a test condition. h half-carry flag (flags.2) the h bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. it is used by the decimal adjust (da) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (bcd) result. the h flag is seldom accessed directly by a program. fis fast interrupt status flag (flags.1) the fis bit is set during a fast interrupt cycle and reset during the iret following interrupt servicing. when set, it inhibits all interrupts and causes the fast interrupt return to be executed when the iret instruction is executed. ba bank address flag (flags.0) the ba flag indicates which register bank in the set 1 area of the internal register file is currently selected, bank 0 or bank 1. the ba flag is cleared to "0" (select bank 0) when you execute the sb0 instruction and is set to "1" (select bank 1) when you execute the sb1 instruction.
instruction set s3c 852b/P852B (preliminary spec) 6- 8 instruction set notation table 6-2. flag notation conventions flag description c carry flag z zero flag s sign flag v overflow flag d decimal-adjust flag h half-carry flag 0 cleared to logic zero 1 set to logic one * set or cleared according to operation ? value is unaffected x value is undefined table 6-3. instruction set symbols symbol description dst destination operand src source operand @ indirect register address prefix pc program counter ip instruction pointer flags flags register (d5h) rp register pointer # immediate operand or register address prefix h hexadecimal number suffix d decimal number suffix b binary number suffix opc opcode
s3c852b/P852B (preliminary spec) instruction set 6- 9 table 6-4. instruction notation conventions notation description actual operand range cc condition code see list of condition codes in table 6-6. r working register only rn (n = 0?15) rb bit (b) of working register rn.b (n = 0?15, b = 0?7) r0 bit 0 (lsb) of working register rn (n = 0?15) rr working register pair rrp (p = 0, 2, 4, ..., 14) r register or working register reg or rn (reg = 0?255, n = 0?15) rb bit 'b' of register or working register reg.b (reg = 0?255, b = 0?7) rr register pair or working register pair reg or rrp (reg = 0?254, even number only, where p = 0, 2, ..., 14) ia indirect addressing mode addr (addr = 0?254, even number only) ir indirect working register only @rn (n = 0?15) ir indirect register or indirect working register @rn or @reg (reg = 0?255, n = 0?15) irr indirect working register pair only @rrp (p = 0, 2, ..., 14) irr indirect register pair or indirect working register pair @rrp or @reg (reg = 0?254, even only, where p = 0, 2, ..., 14) x indexed addressing mode #reg [rn] (reg = 0?255, n = 0?15) xs indexed (short offset) addressing mode #addr [rrp] (addr = range ?128 to +127, where p = 0, 2, ..., 14) xl indexed (long offset) addressing mode #addr [rrp] (addr = range 0?65535, where p = 0, 2, ..., 14) da direct addressing mode addr (addr = range 0?65535) ra relative addressing mode addr (addr = number in the range +127 to ?128 that is an offset relative to the address of the next instruction) im immediate addressing mode #data (data = 0?255) iml immediate (long) addressing mode #data (data = range 0?65535)
instruction set s3c 852b/P852B (preliminary spec) 6- 10 table 6-5. opcode quick reference opcode map lower nibble (hex) ? 0 1 2 3 4 5 6 7 u 0 dec r1 dec ir1 add r1, r2 add r1, ir2 add r2, r1 add ir2, r1 add r1, im bor r0?rb p 1 rlc r1 rlc ir1 adc r1, r2 adc r1, ir2 adc r2, r1 adc ir2, r1 adc r1, im bcp r1.b, r2 p 2 inc r1 inc ir1 sub r1, r2 sub r1, ir2 sub r2, r1 sub ir2, r1 sub r1, im bxor r0?rb e 3 jp irr1 srp/0/1 im sbc r1, r2 sbc r1, ir2 sbc r2, r1 sbc ir2, r1 sbc r1, im btjr r2.b, ra r 4 da r1 da ir1 or r1, r2 or r1, ir2 or r2, r1 or ir2, r1 or r1, im ldb r0?rb 5 pop r1 pop ir1 and r1, r2 and r1, ir2 and r2, r1 and ir2, r1 and r1, im bitc r1.b n 6 com r1 com ir1 tcm r1, r2 tcm r1, ir2 tcm r2, r1 tcm ir2, r1 tcm r1, im band r0?rb i 7 push r2 push ir2 tm r1, r2 tm r1, ir2 tm r2, r1 tm ir2, r1 tm r1, im bit r1.b b 8 decw rr1 decw ir1 pushud ir1, r2 pushui ir1, r2 mult r2, rr1 mult ir2, rr1 mult im, rr1 ld r1, x, r2 b 9 rl r1 rl ir1 popud ir2, r1 popui ir2, r1 div r2, rr1 div ir2, rr1 div im, rr1 ld r2, x, r1 l a incw rr1 incw ir1 cp r1, r2 cp r1, ir2 cp r2, r1 cp ir2, r1 cp r1, im ldc r1, irr2, xl e b clr r1 clr ir1 xor r1, r2 xor r1, ir2 xor r2, r1 xor ir2, r1 xor r1, im ldc r2, irr2, xl c rrc r1 rrc ir1 cpije ir, r2, ra ldc r1, irr2 ldw rr2, rr1 ldw ir2, rr1 ldw rr1, iml ld r1, ir2 h d sra r1 sra ir1 cpijne irr, r2, ra ldc r2, irr1 call ia1 ld ir1, im ld ir1, r2 e e rr r1 rr ir1 ldcd r1, irr2 ldci r1, irr2 ld r2, r1 ld r2, ir1 ld r1, im ldc r1, irr2, xs x f swap r1 swap ir1 ldcpd r2, irr1 ldcpi r2, irr1 call irr1 ld ir2, r1 call da1 ldc r2, irr1, xs
s3c852b/P852B (preliminary spec) instruction set 6- 11 table 6-5. opcode quick reference (continued) opcode map lower nibble (hex) ? 8 9 a b c d e f u 0 ld r1, r2 ld r2, r1 djnz r1, ra jr cc, ra ld r1, im jp cc da inc r1 next p 1 enter p 2 exit e 3 wfi r 4 sb0 5 sb1 n 6 idle i 7 stop b 8 di b 9 ei l a ret e b iret c rcf h d scf e e ccf x f ld r1, r2 ld r2, r1 djnz r1, ra jr cc, ra ld r1, im jp cc, da inc r1 nop
instruction set s3c 852b/P852B (preliminary spec) 6- 12 condition codes the opcode of a conditional jump always contains a 4-bit field called the condition code (cc). this specifies under which conditions it is to execute the jump. for example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. condition codes are listed in table 6-6. the carry (c), zero (z), sign (s), and overflow (v) flags are used to control the operation of conditional jump instructions. table 6-6. condition codes binary mnemonic description flags set 0000 f always false ? 1000 t always true ? 0111 (note) c carry c = 1 1111 (note) nc no carry c = 0 0110 (note) z zero z = 1 1110 (note) nz not zero z = 0 1101 pl plus s = 0 0101 mi minus s = 1 0100 ov overflow v = 1 1100 nov no overflow v = 0 0110 (note) eq equal z = 1 1110 (note) ne not equal z = 0 1001 ge greater than or equal (s xor v) = 0 0001 lt less than (s xor v) = 1 1010 gt greater than (z or (s xor v)) = 0 0010 le less than or equal (z or (s xor v)) = 1 1111 (note) uge unsigned greater than or equal c = 0 0111 (note) ult unsigned less than c = 1 1011 ugt unsigned greater than (c = 0 and z = 0) = 1 0011 ule unsigned less than or equal (c or z) = 1 notes: 1. it indicates condition codes that are related to two different mnemonics but which test the same flag. for example, z and eq are both true if the zero flag (z) is set, but after an add instruction, z would probably be used; after a cp instruction, however, eq would probably be used. 2. for operations involving unsigned numbers, the special condition codes uge, ult, ugt, and ule must be used.
s3c852b/P852B (preliminary spec) instruction set 6- 13 instruction descriptions this section contains detailed information and programming examples for each instruction in the sam8 instruction set. information is arranged in a consistent format for improved readability and for fast referencing. the following information is included in each instruction description: ? instruction name (mnemonic) ? full instruction name ? source/destination format of the instruction operand ? shorthand notation of the instruction's operation ? textual description of the instruction's effect ? specific flag settings affected by the instruction ? detailed description of the instruction's format, e xecution time, and addressing mode(s) ? programming example(s) explaining how to use the instruction
instruction set s3c 852b/P852B (preliminary spec) 6- 14 adc ? add with carry adc dst, src operation: dst ? dst + src + c the source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's- complement addition is performed. in multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 r r 6 15 r ir opc dst src 3 6 16 r im examples: given: r1 = 10h, r2 = 03h, c flag = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: adc r1, r2 ? r1 = 14h, r2 = 03h adc r1, @r2 ? r1 = 1bh, r2 = 03h adc 01h, 02h ? register 01h = 24h, register 02h = 03h adc 01h, @02h ? register 01h = 2bh, register 02h = 03h adc 01h, #11h ? register 01h = 32h in the first example, destination register r1 contains the value 10h, the carry flag is set to "1", and the source working register r2 contains the value 03h. the statement "adc r1, r2" adds 03h and the carry flag value ("1") to the destination value 10h, leaving 14h in register r1.
s3c852b/P852B (preliminary spec) instruction set 6- 15 add ? add add dst, src operation: dst ? dst + src the source operand is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if a carry from the low-order nibble occurred. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 r r 6 05 r ir opc dst src 3 6 06 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: add r1, r2 ? r1 = 15h, r2 = 03h add r1, @r2 ? r1 = 1ch, r2 = 03h add 01h, 02h ? register 01h = 24h, register 02h = 03h add 01h, @02h ? register 01h = 2bh, regi ster 02h = 03h add 01h, #25h ? register 01h = 46h in the first example, destination working register r1 contains 12h and the source working register r2 contains 03h. the statement "add r1, r2" adds 03h to 12h, leaving the value 15h in register r1.
instruction set s3c 852b/P852B (preliminary spec) 6- 16 and ? logical and and dst, src operation: dst ? dst and src the source operand is logically anded with the destination operand. the result is stored in the destination. the and operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. the contents of the source are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 r r 6 55 r ir opc dst src 3 6 56 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: and r1, r2 ? r1 = 02h, r2 = 03h and r1, @r2 ? r1 = 02h, r2 = 03h and 01h, 02h ? register 01h = 01h, register 02h = 03h and 01h, @02h ? register 01h = 00h, register 02h = 03h and 01h, #25h ? register 01h = 21h in the first example, destination working register r1 contains the value 12h and the source working register r2 contains 03h. the statement "and r1, r2" logically ands the source operand 03h with the destination operand value 12h, leaving the value 02h in register r1.
s3c852b/P852B (preliminary spec) instruction set 6- 17 band ? bit and band dst, src.b band dst.b, src operation: dst (0) ? dst (0) and src (b) or dst (b) ? dst (b) and src (0) the specified bit of the source (or the destination) is logically anded with the zero bit (lsb) of the destination (or source). the resultant bit is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 67 r0 rb opc src | b | 1 dst 3 6 67 rb r0 note : in the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. examples: given: r1 = 07h and register 01h = 05h: band r1, 01h.1 ? r1 = 06h, register 01h = 05h band 01h.1, r1 ? register 01h = 05h, r1 = 07h in the first example, source register 01h contains the value 05h (00000101b) and destination working register r1 contains 07h (00000111b). the statement "band r1, 01h.1" ands the bit 1 value of the source register ("0") with the bit 0 value of register r1 (destination), leaving the value 06h (00000110b) in register r1.
instruction set s3c 852b/P852B (preliminary spec) 6- 18 bcp ? bit compare bcp dst, src.b operation: dst (0) ? src (b) the specified bit of the source is compared to (subtracted from) bit zero (lsb) of the destination. the zero flag is set if the bits are the same; otherwise it is cleared. the contents of both operands are unaffected by the comparison. flags: c: unaffected. z: set if the two bits are the same; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 17 r0 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h and register 01h = 01h: bcp r1, 01h.1 ? r1 = 07h, register 01h = 01h if destination working register r1 contains the value 07h (00000111b) and the source register 01h contains the value 01h (00000001b), the statement "bcp r1, 01h.1" compares bit one of the source register (01h) and bit zero of the destination register (r1). because the bit values are not identical, the zero flag bit (z) is cleared in the flags register (0d5h).
s3c852b/P852B (preliminary spec) instruction set 6- 19 bitc ? bit complement bitc dst.b operation: dst(b) ? not dst(b) this instruction complements the specified bit within the destination without affecting any other bits in the destination. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 0 2 4 57 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h bitc r1.1 ? r1 = 05h if working register r1 contains the value 07h (00000111b), the statement "bitc r1.1" complements bit one of the destination and leaves the value 05h (00000101b) in register r1. because the result of the complement is not "0", the zero flag (z) in the flags register (0d5h) is cleared.
instruction set s3c 852b/P852B (preliminary spec) 6- 20 bitr ? bit reset bitr dst.b operation: dst(b) ? 0 the bitr instruction clears the specified bit within the destination without affecting any other bits in the destination. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 0 2 4 77 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: bitr r1.1 ? r1 = 05h if the value of working register r1 is 07h (00000111b), the statement "bitr r1.1" clears bit one of the destination register r1, leaving the value 05h (00000101b).
s3c852b/P852B (preliminary spec) instruction set 6- 21 bits ? bit set bits dst.b operation: dst(b) ? 1 the bits instruction sets the specified bit within the destination without affecting any other bits in the destination. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 1 2 4 77 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: bits r1.3 ? r1 = 0fh if working register r1 contains the value 07h (00000111b), the statement "bits r1.3" sets bit three of the destination register r1 to "1", leaving the value 0fh (00001111b).
instruction set s3c 852b/P852B (preliminary spec) 6- 22 bor ? bit or bor dst, src.b bor dst.b, src operation: dst (0) ? dst (0) or src (b) or dst(b) ? dst(b) or src (0) the specified bit of the source (or the destination) is logically ored with bit zero (lsb) of the destination (or the source). the resulting bit value is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 07 r0 rb opc src | b | 1 dst 3 6 07 rb r0 note : in the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit. examples: given: r1 = 07h and register 01h = 03h: bor r1, 01h.1 ? r1 = 07h, register 01h = 03h bor 01h.2, r1 ? register 01h = 07h, r1 = 07h in the first example, destination working register r1 contains the val ue 07h (00000111b) and source register 01h the value 03h (00000011b). the statement "bor r1, 01h.1" logically ors bit one of register 01h (source) with bit zero of r1 (destination). this leaves the same value (07h) in working register r1. in the second example, destination register 01h contains the value 03h (00000011b) and the source working register r1 the value 07h (00000111b). the statement "bor 01h.2, r1" logically ors bit two of register 01h (destination) with bit zero of r1 (source). this leaves the value 07h in register 01h.
s3c852b/P852B (preliminary spec) instruction set 6- 23 btjrf ? bit test, jump relative on false btjrf dst, src.b operation: if src (b) is a "0", then pc ? pc + dst the specified bit within the source operand is tested. if it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the pc; otherwise, the instruction following the btjrf instruction is executed. flags: no flags are affected. format: (note 1) bytes cycles opcode (hex) addr mode dst src opc src | b | 0 dst 3 10 37 ra rb note: in the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: btjrf skip, r1.3 ? pc jumps to skip location if working register r1 contains the value 07h (00000111b), the statement "btjrf skip, r1.3" tests bit 3. because it is "0", the relative address is added to the pc and the pc jumps to the memory location pointed to by the skip. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
instruction set s3c 852b/P852B (preliminary spec) 6- 24 btjrt ? bit test, jump relative on true btjrt dst, src.b operation: if src (b) is a "1", then pc ? pc + dst the specified bit within the source operand is tested. if it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the pc; otherwise, the instruction following the btjrt instruction is executed. flags: no flags are affected. format: (note 1) bytes cycles opcode (hex) addr mode dst src opc src | b | 1 dst 3 10 37 ra rb note: in the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: btjrt skip, r1.1 if working register r1 contains the value 07h (00000111b), the statement "btjrt skip, r1.1" tests bit one in the source register (r1). because it is a "1", the relative address is added to the pc and the pc jumps to the memory location pointed to by the skip. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
s3c852b/P852B (preliminary spec) instruction set 6- 25 bxor ? bit xor bxor dst, src.b bxor dst.b, src operation: dst (0) ? dst (0) xor src (b) or dst(b) ? dst(b) xor src (0) the specified bit of the source (or the destination) is logically exclusive-ored with bit zero (lsb) of the destination (or source). the result bit is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 27 r0 rb opc src | b | 1 dst 3 6 27 rb r0 note : in the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. examples: given: r1 = 07h (00000111b) and register 01h = 03h (00000011b): bxor r1, 01h.1 ? r1 = 06h, register 01h = 03h bxor 01h.2, r1 ? register 01h = 07h, r1 = 07h in the first example, destination working register r1 has the value 07h (00000111b) and source register 01h has the value 03h (00000011b). the statement "bxor r1, 01h.1" exclusive-ors bit one of register 01h (source) with bit zero of r1 (destination). the result bit value is stored in bit zero of r1, changing its value from 07h to 06h. the value of source register 01h is unaffected.
instruction set s3c 852b/P852B (preliminary spec) 6- 26 call ? call procedure call dst operation: sp ? sp ? 1 @sp ? pcl sp ? sp ?1 @sp ? pch pc ? dst the current contents of the program counter are pushed onto the top of the stack. the program counter value used is the address of the first instruction following the call instruction. the specified destination address is then loaded into the program counter and points to the first instruction of a procedure. at the end of the procedure the return instruction (ret) can be used to return to the original program flow. ret pops the top of the stack back into the program counter. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 3 14 f6 da opc dst 2 12 f4 irr opc dst 2 14 d4 ia examples: given: r0 = 35h, r1 = 21h, pc = 1a47h, and sp = 0002h: call 3521h ? sp = 0000h (memory locatio ns 0000h = 1ah, 0001h = 4ah, where 4ah is the address that follows the instruction.) call @rr0 ? sp = 0000h (0000h = 1ah, 0001h = 49h) call #40h ? sp = 0000h (0000h = 1ah, 0001h = 49h) in the first example, if the program counter value is 1a47h and the stack pointer contains the value 0002h, the statement "call 3521h" pushes the current pc value onto the top of the stack. the stack pointer now points to memory location 0000h. the pc is then loaded with the value 3521h, the address of the first instruction in the program sequence to be executed. if the contents of the program counter and stack pointer are the same as in the first example, the statement "call @rr0" produces the same result except that the 49h is stored in stack location 0001h (because the two-byte instruction format was used). the pc is then loaded with the value 3521h, the address of the first instruction in the program sequence to be executed. assuming that the contents of the program counter and stack pointer are the same as in the first example, if program address 0040h contains 35h and program address 0041h contains 21h, the statement "call #40h" produces the same result as in the second example.
s3c852b/P852B (preliminary spec) instruction set 6- 27 ccf ? complement carry flag ccf operation: c ? not c the carry flag (c) is complemented. if c = "1", the value of the carry flag is changed to logic zero; if c = "0", the value of the carry flag is changed to logic one. flags: c: complemented. no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 ef example: given: the carry flag = "0": ccf if the carry flag = "0", the ccf instruction complements it in the flags register (0d5h), changing its value from logic zero to logic one.
instruction set s3c 852b/P852B (preliminary spec) 6- 28 clr ? clear clr dst operation: dst ? "0" the destination location is cleared to "0". flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 b0 r 4 b1 ir examples: given: register 00h = 4fh, register 01h = 02h, and regist er 02h = 5eh: clr 00h ? register 00h = 00h clr @01h ? register 01h = 02h, register 02h = 00h in register (r) addressing mode, the statement "clr 00h" clears the destination register 00h value to 00h. in the second example, the statement "clr @01h" uses indirect register (ir) addressing mode to clear the 02h register value to 00h.
s3c852b/P852B (preliminary spec) instruction set 6- 29 com ? complement com dst operation: dst ? not dst the contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 60 r 4 61 ir examples: given: r1 = 07h and register 07h = 0f1h: com r1 ? r1 = 0f8h com @r1 ? r1 = 07h, register 07h = 0eh in the first example, destination working register r1 contains the value 07h (00000111b) . the statement "com r1" complements all the bits in r1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0f8h (11111000b). in the second example, indirect register (ir) addressing mode is used to complement the value of destination register 07h (11110001b), leaving the new value 0eh (00001110b).
instruction set s3c 852b/P852B (preliminary spec) 6- 30 cp ? compare cp dst, src operation: dst ? src the source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. the contents of both operands are unaffected by the comparison. flags: c: set if a "borrow" occurred (src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 a2 r r 6 a3 r lr opc src dst 3 6 a4 r r 6 a5 r ir opc dst src 3 6 a6 r im examples: 1. given: r1 = 02h and r2 = 03h: cp r1, r2 ? set the c and s flags destination working register r1 contains the value 02h and source register r2 contains the value 03h. the statement "cp r1, r2" subtracts the r2 value (source/subtrahend) from the r1 value (destination/minuend). because a "borrow" occurs and the difference is negative, c and s are "1". 2. given: r1 = 05h and r2 = 0ah: cp r1, r2 jp uge, skip inc r1 skip ld r3, r1 in this example, destinati on working register r1 contains the value 05h which is less than the contents of the source working register r2 (0ah). the statement "cp r1, r2" generates c = "1" and the jp instruction does not jump to the skip location. after the statement "ld r3, r1" executes, the value 06h remains in working register r3.
s3c852b/P852B (preliminary spec) instruction set 6- 31 cpije ? compare, increment, and jump on equal cpije dst, src, ra operation: if dst ? src = "0", pc ? pc + ra ir ? ir + 1 the source operand is compared to (subtracted f rom) the destination operand. if the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. otherwise, the instruction immediately following the cpije instruction is executed. in either case, the source pointer is incremented by one before the next instruction is executed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst ra 3 12 c2 r ir note: execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. example: given: r1 = 02h, r2 = 03h, and register 03h = 02h: cpije r1, @r2, skip ? r2 = 04h, pc jumps to skip location in this example, working register r1 contains the value 02h, working register r2 the value 03h, and register 03 contains 02h. the statement "cpije r1, @r2, skip" compares the @r2 value 02h (00000010b) to 02h (00000010b). because the result of the comparison is equal , the relative address is added to the pc and the pc then jumps to the memory location pointed to by skip. the source register (r2) is incremented by one, leaving a value of 04h. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
instruction set s3c 852b/P852B (preliminary spec) 6- 32 cpijne ? compare, increment, and jump on non-equal cpijne dst, src, ra operation: if dst ? src ? "0", pc ? pc + ra ir ? ir + 1 the source operand is compared to (subtracted from) the destination operand. if the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise the instruction following the cpijne instruction is executed. in either case the source pointer is incremented by one before the next instruction. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst ra 3 12 d2 r ir note: execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. example: given: r1 = 02h, r2 = 03h, and register 03h = 04h: cpijne r1, @r2, skip ? r2 = 04h, pc jumps to skip location working register r1 contains the value 02h, working register r2 (the source pointer) the value 03h, and general register 03 the value 04h. the statement "cpijne r1, @r2, skip" subtracts 04h (00000100b) from 02h (00000010b). because the result of the comparison is non-equal , the relative address is added to the pc and the pc then jumps to the memory location pointed to by skip. the source pointer register (r2) is also incremented by one, leaving a value of 04h. (remember that the memory location must be within the allowed range of + 127 to ? 128.)
s3c852b/P852B (preliminary spec) instruction set 6- 33 da ? decimal adjust da dst operation: dst ? da dst the destination operand is adjusted to form two 4-bit bcd digits following an addition or subtraction operation. for addition (add, adc) or subtraction (sub, sbc), the following table indicates the operation performed. (the operation is undefined if the destination operand was not the result of a valid addition or subtraction of bcd digits): instruction carry before da bits 4?7 value (hex) h flag before da bits 0?3 value (hex) number added to byte carry after da 0 0?9 0 0?9 00 0 0 0?8 0 a?f 06 0 0 0?9 1 0?3 06 0 add 0 a?f 0 0?9 60 1 adc 0 9?f 0 a?f 66 1 0 a?f 1 0?3 66 1 1 0?2 0 0?9 60 1 1 0?2 0 a?f 66 1 1 0?3 1 0?3 66 1 0 0?9 0 0?9 00 = ? 00 0 sub 0 0?8 1 6?f fa = ? 06 0 sbc 1 7?f 0 0?9 a0 = ? 60 1 1 6?f 1 6?f 9a = ? 66 1 flags: c: set if there was a carry from the most significant bit; cleared otherwise (see table). z: set if result is "0"; cleared otherwise. s: set if result bit 7 is set; cleared otherwise. v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 40 r 4 41 ir
instruction set s3c 852b/P852B (preliminary spec) 6- 34 da ? decimal adjust da (continued) example: given: working register r0 contains the value 15 (bcd), working register r1 contains 27 (bcd), and address 27h contains 46 (bcd): add r1, r0 ; c ? "0", h ? "0", bits 4?7 = 3, bits 0?3 = c, r1 ? 3ch da r1 ; r1 ? 3ch + 06 if addition is performed using the bcd values 15 and 27, the result should be 42. the sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic: 0 0 0 1 0 1 0 1 15 + 0 0 1 0 0 1 1 1 27 0 0 1 1 1 1 0 0 = 3ch the da instruction adjusts this result so that the correct bcd representation is obtained: 0 0 1 1 1 1 0 0 + 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 = 42 assuming the same values given above, the statements sub 27h, r0 ; c ? "0", h ? "0", bits 4?7 = 3, bits 0?3 = 1 da @r1 ; @r1 ? 31?0 leave the value 31 (bcd) in address 27h (@r1).
s3c852b/P852B (preliminary spec) instruction set 6- 35 dec ? decrement dec dst operation: dst ? dst ? 1 the contents of the destination operand are decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 00 r 4 01 ir examples: given: r1 = 03h and register 03h = 10h: dec r1 ? r1 = 02h dec @r1 ? register 03h = 0fh in the first example, if working register r1 contains the value 03h, the statement "dec r1" decrements the hexadecimal value by one, leaving the value 02h. in the second example, the statement "dec @r1" decrements the value 10h contained in the destination register 03h by one, leaving the value 0fh.
instruction set s3c 852b/P852B (preliminary spec) 6- 36 decw ? decrement word decw dst operation: dst ? dst ? 1 the contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 80 rr 8 81 ir examples: given: r0 = 12h, r1 = 34h, r2 = 30h, register 30h = 0fh, and register 31h = 21h: decw rr0 ? r0 = 12h, r1 = 33h decw @r2 ? register 30h = 0fh, register 31h = 20h in the first example, destination register r0 contains the value 12h and register r1 the value 34h. the statement "decw rr0" addresses r0 and the following operand r1 as a 16-bit word and decrements the value of r1 by one, leaving the value 33h. note: a system malfunction may occur if you use a zero flag (flags.6) result together with a decw instruction. to avoid this problem, we recommend that you use decw as shown in the following example: loop: decw rr0 ld r2, r1 or r2, r0 jr nz, loop
s3c852b/P852B (preliminary spec) instruction set 6- 37 di ? disable interrupts di operation: sym (0) ? 0 bit zero of the system mode control register, sym.0, is cleared to "0", globally disabling all interrupt processing. interrupt requests will continue to set their respective interrupt pending bits, but the cpu will not service them while interrupt processing is disabled. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 8f example: given: sym = 01h: di if the value of the sym register is 01h, the statement "di" leaves the new value 00h in the register and clears sym.0 to "0", disabling interrupt processing. before changing imr, interrupt pending and interrupt source control register, be sure di state.
instruction set s3c 852b/P852B (preliminary spec) 6- 38 div ? divide (unsigned) div dst, src operation: dst src dst (upper) ? remainder dst (lower) ? quotient the destination operand (16 bits) is divided by the source operand (8 bits). the quotient (8 bits) is stored in the lower half of the destination. the remainder (8 bits) is stored in the upper half of the destination. when the quotient is 3 2 8 , the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. both operands are treated as unsigned integers. flags: c: set if the v flag is set and quotient is between 2 8 and 2 9 ?1; cleared otherwise. z: set if divisor or quotient = "0"; cleared otherwise. s: set if msb of quotient = "1"; cleared otherwise. v: set if quotient is 3 2 8 or if divisor = "0"; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 26/10 94 rr r 26/10 95 rr ir 26/10 96 rr im note: execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles. examples: given: r0 = 10h, r1 = 03h, r2 = 40h, register 40h = 80h: div rr0, r2 ? r0 = 03h, r1 = 40h div rr0, @r2 ? r0 = 03h, r1 = 20h div rr0, #20h ? r0 = 03h, r1 = 80h in the first example, destination working register pair rr0 contains the values 10h (r0) and 03h (r1), and register r2 contains the value 40h. the statement "div rr0, r2" divides the 16-bit rr0 value by the 8-bit value of the r2 (source) register. after the div instruction, r0 contains the value 03h and r1 contains 40h. the 8-bit remainder is stored in the upper half of the destination register rr0 (r0) and the quotient in the lower half (r1).
s3c852b/P852B (preliminary spec) instruction set 6- 39 djnz ? decrement and jump if non-zero djnz r, dst operation: r ? r ? 1 if r 1 0, pc ? pc + dst the working register being used as a counter is decremented. if the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the pc. the range of the relative address is +127 to ?128, and the original value of the pc is taken to be the address of the instruction byte following the djnz statement. note: in case of using djnz instruction, the working register being used as a counter should be set at the one of location 0c0h to 0cfh with srp, srp0, or srp1 instruction. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst r | opc dst 2 8 (jump taken) ra ra 8 (no jump) r = 0 to f example: given: r1 = 02h and loop is the label of a relative address: srp #0c0h djnz r1, loop djnz is typically used to control a "loop" of instructions. in many cases, a label is used as the destination operand instead of a numeric relative address value. in the example, working register r1 contains the value 02h, and loop is the label for a relative address. the statement "djnz r1, loop" decrements register r1 by one, leaving the value 01h. because the contents of r1 after the decrement are non-zero, the jump is taken to the relative address specified by the loop label.
instruction set s3c 852b/P852B (preliminary spec) 6- 40 ei ? enable interrupts ei operation: sym (0) ? 1 an ei instruction sets bit zero of the system mode register, sym.0 to "1". this allows interrupts to be serviced as they occur (assuming they have highest priority). if an interrupt's pending bit was set while interrupt processing was disabled (by executing a di instruction), it will be serviced when you execute the ei instruction. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 9f example: given: sym = 00h: ei if the sym register contains the value 00h, that is, if interrupts are currently disabled, the statement "ei" sets the sym register to 01h, enabling all interrupts. (sym.0 is the enable bit for global interrupt processing.)
s3c852b/P852B (preliminary spec) instruction set 6- 41 enter ? enter enter operation: sp ? sp ? 2 @sp ? ip ip ? pc pc ? @ip ip ? ip + 2 this instruction is useful when implementing threaded-code lan guages. the contents of the instruction pointer are pushed to the stack. the program counter (pc) value is then written to the instruction pointer. the program memory word that is pointed to by the instruction pointer is loaded into the pc, and the instruction pointer is incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 14 1f example: the diagram below shows one example of how to use an enter statement. 0050 1p 0022 sp 22 data address data 0040 pc 40 41 42 43 enter address h address l address h address data 1f 01 10 memory 0043 1p 0020 sp 20 21 22 iph ipl data address data 0110 pc 40 41 42 43 enter address h address l address h address data 1f 01 10 memory 00 50 stack stack 110 routine before after
instruction set s3c 852b/P852B (preliminary spec) 6- 42 exit ? exit exit operation: ip ? @sp sp ? sp + 2 pc ? @ip ip ? ip + 2 this instruction is useful when implementing threaded-code languages. the stack value is popped and loaded into the instruction pointer. the program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 14 (internal stack) 2f 16 (internal stack) example: the diagram below shows one example of how to use an exit statement. 0050 1p 0022 sp address data 0040 pc address data memory 0052 1p 0022 sp address data 0060 pc address data memory stack stack before after 22 data 20 21 22 iph ipl data 00 50 50 51 140 pcl old pch exit 60 00 2f 60 main
s3c852b/P852B (preliminary spec) instruction set 6- 43 idle ? idle operation idle operation: the idle instruction stops the cpu clock while allowing system clock oscillation to continue. idle mode can be released by an interrupt request (irq) or an external reset operation. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 6f example: the instruction idle stops the cpu clock but not the system clock
instruction set s3c 852b/P852B (preliminary spec) 6- 44 inc ? increment inc dst operation: dst ? dst + 1 the contents of the destination operand are incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst dst | opc 1 4 re r r = 0 to f opc dst 2 4 20 r 4 21 ir examples: given: r0 = 1bh, register 00h = 0ch, and register 1bh = 0fh: inc r0 ? r0 = 1ch inc 00h ? register 00h = 0dh inc @r0 ? r0 = 1bh, register 01h = 10h in the first example, if destination working register r0 contains the value 1bh, the statement "inc r0" leaves the value 1ch in that same register. the next example shows the effect an inc instruction has on register 00h, assuming that it contains the value 0ch. in the third example, inc is used in indirect register (ir) addressing mode to incr ement the value of register 1bh from 0fh to 10h.
s3c852b/P852B (preliminary spec) instruction set 6- 45 incw ? increment word incw dst operation: dst ? dst + 1 the contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 a0 rr 8 a1 ir examples: given: r0 = 1ah, r1 = 02h, register 02h = 0fh, and register 03h = 0ffh: incw rr0 ? r0 = 1ah, r1 = 03h incw @r1 ? register 02h = 10h, register 03h = 00h in the first example, the working register pair rr0 contains the value 1ah in register r0 and 02h in register r1. the statement "incw rr0" increments the 16-bit destination by one, leaving the value 03h in register r1. in the second example, the statement "incw @r1" uses indirect register (ir) addressing mode to increment the contents of general register 03h from 0ffh to 00h and register 02h from 0fh to 10h. note: a system malfunction may occur if you use a zero (z) flag (flags.6) result together with an incw instruction. to avoid this problem, we recommend that you use incw as shown in the following example: loop: incw rr0 ld r2, r1 or r2, r0 jr nz, loop
instruction set s3c 852b/P852B (preliminary spec) 6- 46 iret ? interrupt return iret iret (normal) iret (fast) operation: flags ? @sp pc ? ip sp ? sp + 1 flags ? flags' pc ? @sp fis ? 0 sp ? sp + 2 sym(0) ? 1 this instruction is used at the end of an interrupt service routine. it restores the flag register and the program counter. it also re-enables global interrupts. a "normal iret" is executed only if the fast interrupt status bit (fis, bit one of the flags register, 0d5h) is cleared (= "0"). if a fast interrupt occurred, iret clears the fis bit that was set at the beginning of the service routine. flags: all flags are restored to their original settings (that is, the settings before the interrupt occurred). format: iret (normal) bytes cycles opcode (hex) opc 1 10 (internal stack) bf 12 (internal stack) iret (fast) bytes cycles opcode (hex) opc 1 6 bf example: in the figure below, the instruction pointer is initially loaded with 100h in the main program before interrupts are enabled. when an interrupt occurs, the program counter and instruction pointer are swapped. this causes the pc to jump to address 100h and the ip to keep the return address. the last instruction in the service routine normally is a jump to iret at address ffh. this causes the instruction pointer to be loaded with 100h "again" and the program counter to jump back to the main program. now, the next interrupt can occur and the ip is still correct at 100h. iret interrupt service routine jp to ffh 0h ffh 100h ffffh note in the fast interrupt example above, if the last instruction is not a jump to iret, you must pay attention to the order of the last two instructions. the iret cannot be immediately proceeded by a clearing of the interrupt status (as with a reset of the ipr register).
s3c852b/P852B (preliminary spec) instruction set 6- 47 jp ? jump jp cc, dst (conditional) jp dst (unconditional) operation: if cc is true, pc ? dst the conditional jump instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the jp instruction is executed. the unconditional jp simply replaces the contents of the pc with the contents of the specified register pair. control then passes to the statement addressed by the pc. flags: no flags are affected. format: (1) (2) bytes cycles opcode (hex) addr mode dst cc | opc dst 3 8 ccd da cc = 0 to f opc dst 2 8 30 irr notes : 1. the 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. in the first byte of the three-byte instruction format (conditional jump) , the condition code and the opcode are both four bits. examples: given: the carry flag (c) = "1", register 00 = 01h, and register 01 = 20h: jp c, label_w ? label_w = 1000h, pc = 1000h jp @00h ? pc = 0120h the first example shows a conditional jp. assuming that the carry flag is set to "1", the statement "jp c, label_w" replaces the contents of the pc with the value 1000h and transfers control to that location. had the carry flag not been set, control would then have passed to the statement immediately following the jp instruction. the second example shows an unconditional jp. the statement "jp @00" replaces the contents of the pc with the contents of the register pair 00h and 01h, leaving the value 0120h.
instruction set s3c 852b/P852B (preliminary spec) 6- 48 jr ? jump relative jr cc, dst operation: if cc is true, pc ? pc + dst if the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the jr instruction is executed. (see list of condition codes). the range of the relative address is +127, ?128, and the original value of the program counter is taken to be the address of the first instruction byte following the jr statement. flags: no flags are affected. format: (1) bytes cycles opcode (hex) addr mode dst cc | opc dst 2 6 ccb ra cc = 0 to f note : in the first byte of the two-byte instruction format, the condition code and the opcode are each four bits. example: given: the carry flag = "1" and label_x = 1ff7h: jr c, label_x ? pc = 1ff7h if the carry flag is set (that is, if the condition code is true), the statement "jr c, label_x" will pass control to the statement whose address is now in the pc. otherwise, the program instruction following the jr would be executed.
s3c852b/P852B (preliminary spec) instruction set 6- 49 ld ? load ld dst, src operation: dst ? src the contents of the source are loaded into the destination. the source's contents are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src dst | opc src 2 4 rc r im 4 r8 r r src | opc dst 2 4 r9 r r r = 0 to f opc dst | src 2 4 c7 r lr 4 d7 ir r opc src dst 3 6 e4 r r 6 e5 r ir opc dst src 3 6 e6 r im 6 d6 ir im opc src dst 3 6 f5 ir r opc dst | src x 3 6 87 r x [r] opc src | dst x 3 6 97 x [r] r
instruction set s3c 852b/P852B (preliminary spec) 6- 50 ld ? load ld (continued) examples: given: r0 = 01h, r1 = 0ah, register 00h = 01h, register 01h = 20h, register 02h = 02h, loop = 30h, and register 3ah = 0ffh: ld r0, #10h ? r0 = 10h ld r0, 01h ? r0 = 20h, register 01h = 20h ld 01h, r0 ? register 01h = 01h, r0 = 01h ld r1, @r0 ? r1 = 20h, r0 = 01h ld @r0, r1 ? r0 = 01h, r1 = 0ah, register 01h = 0ah ld 00h, 01h ? register 00h = 20h, register 01h = 20h ld 02h, @00h ? regist er 02h = 20h, register 00h = 01h ld 00h, #0ah ? register 00h = 0ah ld @00h, #10h ? register 00h = 01h, register 01h = 10h ld @00h, 02h ? register 00h = 01h, register 01h = 02, register 02h = 02h ld r0, #loop[r1] ? r0 = 0ffh, r1 = 0ah ld #loop[r0], r1 ? register 31h = 0ah, r0 = 01h, r1 = 0ah
s3c852b/P852B (preliminary spec) instruction set 6- 51 ldb ? load bit ldb dst, src.b ldb dst.b, src operation: dst (0) ? src (b) or dst(b) ? src (0) the specified bit of the source is loaded into bit zero (lsb) of the destination, or bit zero of the source is loaded into the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 47 r0 rb opc src | b | 1 dst 3 6 47 rb r0 note : in the second byte of the instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the lsb address value is one bit in length. examples: given: r0 = 06h and general register 00h = 05h: ldb r0, 00h.2 ? r0 = 07h, register 00h = 05h ldb 00h.0, r0 ? r0 = 06h, register 00h = 04h in the first example, destination working register r0 contains the value 06h and the source general register 00h the value 05h. the statement "ld r0, 00h.2" loads the bit two value of the 00h register into bit zero of the r0 register, leaving the value 07h in register r0. in the second example, 00h is the destination re gister. the statement "ld 00h.0, r0" loads bit zero of register r0 to the specified bit (bit zero) of the destination register, leaving 04h in general register 00h.
instruction set s3c 852b/P852B (preliminary spec) 6- 52 ldc/lde ? load memory ldc/lde dst, src operation: dst ? src this instruction loads a byte from program or data memory into a working register or vice-versa. the source values are unaffected. ldc refers to program memory and lde to data memory. the assembler makes ' irr' or ' rr' values an even number for program memory and odd an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src 1. opc dst | src 2 10 c3 r irr 2. opc src | dst 2 10 d3 irr r 3. opc dst | src xs 3 12 e7 r xs [rr] 4. opc src | dst xs 3 12 f7 xs [rr] r 5. opc dst | src xl l xl h 4 14 a7 r xl [rr] 6. opc src | dst xl l xl h 4 14 b7 xl [rr] r 7. opc dst | 0000 da l da h 4 14 a7 r da 8. opc src | 0000 da l da h 4 14 b7 da r 9. opc dst | 0001 da l da h 4 14 a7 r da 10. opc src | 0001 da l da h 4 14 b7 da r notes : 1. the source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0?1. 2. for formats 3 and 4, the destination address 'xs [rr]' and the source address 'xs [rr]' are each one byte. 3. for formats 5 and 6, the destination address 'xl [rr] and the source address 'xl [rr]' are each two bytes. 4. the da and r source values for f ormats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.
s3c852b/P852B (preliminary spec) instruction set 6- 53 ldc/lde ? load memory ldc/lde (continued) examples: given: r0 = 11h, r1 = 34h, r2 = 01h, r3 = 04h; program memory locations 0103h = 4fh, 0104h = 1a, 0105h = 6dh, and 1104h = 88h. external data memory locations 0103h = 5fh, 0104h = 2ah, 0105h = 7dh, and 1104h = 98h: ldc r0, @rr2 ; r0 ? contents of program memory location 0104h ; r0 = 1ah, r2 = 01h, r3 = 04h lde r0, @rr2 ; r0 ? contents of external data memory location 0104h ; r0 = 2ah, r2 = 01h, r3 = 04h ldc (note) @rr2, r0 ; 11h (contents of r0) is loaded into program memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change lde @rr2, r0 ; 11h (contents of r0) is loaded into external data memory ; location 0104h (rr2), ; working registers r0, r2, r3 ? no change ldc r0, #01h[rr2] ; r0 ? contents of program memory location 0105h ; (01h + rr2), ; r0 = 6dh, r2 = 01h, r3 = 04h lde r0, #01h[rr2] ; r0 ? contents of external data memory location 0105h ; (01h + rr2), r0 = 7dh, r2 = 01h, r3 = 04h ldc (note) #01h[rr2], r0 ; 11h (contents of r0) is loaded into program memory location ; 0105h (01h + 0104h) lde #01h[rr2], r0 ; 11h (contents of r0) is loaded into external data memory ; location 0105h (01h + 0104h) ldc r0, #1000h[rr2] ; r0 ? contents of program memory location 1104h ; (1000h + 0104h), r0 = 88h, r2 = 01h, r3 = 04h lde r0, #1000h[rr2] ; r0 ? contents of external data memory location 1104h ; (1000h + 0104h), r0 = 98h, r2 = 01h, r3 = 04h ldc r0, 1104h ; r0 ? contents of program memory location 1104h, r0 = 88h lde r0, 1104h ; r0 ? contents of external data memory location 1104h, ; r0 = 98h ldc (note) 1105h, r0 ; 11h (contents of r0) is loaded into program memory location ; 1105h, (1105h) ? 11h lde 1105h, r0 ; 11h (contents of r0) is loaded into external data memory ; location 1105h, (110 5h) ? 11h note: these instructions are not supported by masked rom type devices.
instruction set s3c 852b/P852B (preliminary spec) 6- 54 ldcd/lded ? load memory and decrement ldcd/lded dst, src operation: dst ? src rr ? rr ? 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then decremented. the contents of the source are unaffected. ldcd references program memory and lded references external data memory. the assembler makes 'irr' an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e2 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory location 1033h = 0cdh, and external data memory location 1033h = 0ddh: ldcd r8, @rr6 ; 0 cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is decremented by one ; r8 = 0cdh, r6 = 10h, r7 = 32h (rr6 ? rr6 ? 1) lded r8, @rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; into r8 and rr6 is decremented by one (rr6 ? rr6 ? 1) ; r8 = 0ddh, r6 = 10h, r7 = 32h
s3c852b/P852B (preliminary spec) instruction set 6- 55 ldci/ldei ? load memory and increment ldci/ldei dst, src operation: dst ? src rr ? rr + 1 these instructions are used for user stacks or block trans fers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then incremented automatically. the contents of the source are unaffected. ldci refers to program memory and ldei refers to external data memory. the assembler makes 'irr' even for program memory and odd for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e3 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory locations 1033h = 0cdh and 1034h = 0c5h; external data memory locations 1033h = 0ddh and 1034h = 0d5h: ldci r8, @rr6 ; 0cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is incremented by one (rr6 ? rr6 + 1) ; r8 = 0cdh, r6 = 10h, r7 = 34h ldei r8, @rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; i nto r8 and rr6 is incremented by one (rr6 ? rr6 + 1) ; r8 = 0ddh, r6 = 10h, r7 = 34h
instruction set s3c 852b/P852B (preliminary spec) 6- 56 ldcpd/ldepd ? load memory with pre-decrement ldcpd/ ldepd dst, src operation: rr ? rr ? 1 dst ? src these instructions are used for block transfers of data from program or data memory from the register file. the address of the memory location is specified by a working register pair and is first decremented. the contents of the source location are then loaded into the destination location. the contents of the source are unaffected. ldcpd refers to program memory and ldepd refers to external data memory. the assembler makes 'irr' an even number for program memory and an odd number for external data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src | dst 2 14 f2 irr r examples: given: r0 = 77h, r6 = 30h, and r7 = 00h: ldcpd @rr6, r0 ; (rr6 ? rr6 ? 1) ; 77h (contents of r0) is loaded into program memory locat ion ; 2fffh (3000h ? 1h) ; r0 = 77h, r6 = 2fh, r7 = 0ffh ldepd @rr6, r0 ; (rr6 ? rr6 ? 1) ; 77h (contents of r0) is loaded into external data memory ; location 2fffh (3000h ? 1h) ; r0 = 77h, r6 = 2fh, r7 = 0ffh
s3c852b/P852B (preliminary spec) instruction set 6- 57 ldcpi/ldepi ? load memory with pre-increment ldcpi/ ldepi dst, src operation: rr ? rr + 1 dst ? src these instructions are used for block transfers of data from program or data memory from the register file. the address of the memory location is specified by a working register pair and is first incremented. the contents of the source location are loaded into the destination location. the contents of the source are unaffected. ldcpi refers to program memory and ldepi refers to external data memory. the assembler makes 'irr' an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src | dst 2 14 f3 irr r examples: given: r0 = 7 fh, r6 = 21h, and r7 = 0ffh: ldcpi @rr6, r0 ; (rr6 ? rr6 + 1) ; 7fh (contents of r0) is loaded into program memory ; location 2200h (21ffh + 1h) ; r0 = 7fh, r6 = 22h, r7 = 00h ldepi @rr6, r0 ; (rr6 ? rr6 + 1) ; 7fh (contents of r0) is loaded into external data memory ; location 2200h (21ffh + 1h) ; r0 = 7fh, r6 = 22h, r7 = 00h
instruction set s3c 852b/P852B (preliminary spec) 6- 58 ldw ? load word ldw dst, src operation: dst ? src the contents of the source (a word) are loaded into the destination. the contents of the source are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 c4 rr rr 8 c5 rr ir opc dst src 4 8 c6 rr iml examples: given: r4 = 06h, r5 = 1ch, r6 = 05h, r7 = 02h, register 00h = 1ah, register 01h = 02h, register 02h = 03h, and register 03h = 0fh: ldw rr6, rr4 ? r6 = 06h, r7 = 1ch, r4 = 06h, r5 = 1ch ldw 00h, 02h ? register 00h = 03h, register 01h = 0fh, regi ster 02h = 03h, register 03h = 0fh ldw rr2, @r7 ? r2 = 03h, r3 = 0fh, ldw 04h, @01h ? register 04h = 03h, register 05h = 0fh ldw rr6, #1234h ? r6 = 12h, r7 = 34h ldw 02h, # 0fedh ? register 02h = 0fh, register 03h = 0edh in the second example, please note that the statement "ldw 00h, 02h" loads the contents of the source word 02h, 03h into the destination word 00h, 01h. this leaves the value 03h in general register 00h and the value 0fh in register 01h. the other examples show how to use the ldw instruction with various addressing modes and formats.
s3c852b/P852B (preliminary spec) instruction set 6- 59 mult ? multiply (unsigned) mult dst, src operation: dst ? dst src the 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. both operands are treated as unsigned integers. flags: c: set if result is > 255; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if msb of the result is a "1"; cleared otherwise. v: cleared. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 22 84 rr r 22 85 rr ir 22 86 rr im examples: given: register 00h = 20h, register 01h = 03h, register 02h = 09h, register 03h = 06h: mult 00h, 02h ? register 00h = 01h, register 01h = 20h, register 02h = 09h mult 00h, @01h ? register 00h = 00h, register 01h = 0c0h mult 00h, #30h ? register 00h = 06h, register 01h = 00h in the first example, the statement "mult 00h, 02h" multiplies the 8-bit destination operand (in the register 00h of the register pair 00h, 01h) by the source register 02h operand (09h). the 16 -bit product, 0120h, is stored in the register pair 00h, 01h.
instruction set s3c 852b/P852B (preliminary spec) 6- 60 next ? next next operation: pc ? @ ip ip ? ip + 2 the next instruction is useful when implementing threaded-code languages. the program memory word that is pointed to by the instruction pointer is loaded into the program counter. the instruction pointer is then incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 10 0f example: the following diagram shows one example of how to use the next instruction. data 01 30 before after 0045 1p address data 0130 pc 43 44 45 address h address l address h address data memory 130 routine 0043 1p address data 0120 pc 43 44 45 address h address l address h address data memory 120 next
s3c852b/P852B (preliminary spec) instruction set 6- 61 nop ? no operation nop operation: no action is performed when the cpu executes this instruction. typically, one or more nops are executed in sequence in order to effect a timing delay of variable duration. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 ff example: when the instruction nop is encountered in a program, no operation occurs. instead, there is a delay in instruction execution time.
instruction set s3c 852b/P852B (preliminary spec) 6- 62 or ? logical or or dst, src operation: dst ? dst or src the source operand is logically ored with the destination operand and the result is stored in the destination. the contents of the source are unaffected. the or operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 r r 6 45 r ir opc dst src 3 6 46 r im examples: given: r0 = 15h, r1 = 2ah, r2 = 01h, register 00h = 08h, register 01h = 37h, and register 08h = 8ah: or r0, r1 ? r0 = 3fh, r1 = 2ah or r0, @r2 ? r0 = 37h, r2 = 01h, register 01h = 37h or 00h, 01h ? register 00h = 3fh, register 01h = 37h or 01h, @00h ? register 00h = 08h, register 01h = 0bfh or 00h, #02h ? register 00h = 0ah in the first example, if working register r0 contains the value 15h and register r1 the value 2ah, the statement "or r0, r1" logical-ors the r0 and r1 register contents and stores the result (3fh) in destination register r0. the other examples show the use of the logical or instruction with the various addressing modes and formats.
s3c852b/P852B (preliminary spec) instruction set 6- 63 pop ? pop from stack pop dst operation: dst ? @sp sp ? sp + 1 the contents of the location addressed by the stack pointer are loaded into the destination. the stack pointer is then incremented by one. flags: no flags affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 50 r 8 51 ir examples: given: register 00h = 01h, register 01h = 1bh, sph (0d8h) = 00h, spl (0d9h) = 0fbh, and stack register 0fbh = 55h: pop 00h ? register 00h = 55h, sp = 00fch pop @00h ? register 00h = 01h, register 01h = 55h, sp = 00fch in the first example, general register 00h contains the value 01h. the statement "pop 00h" loads the contents of location 00fbh (55h) into destination register 00h and then increments the stack pointer by one. register 00h then contains the value 55h and the sp points to location 00fch.
instruction set s3c 852b/P852B (preliminary spec) 6- 64 popud ? pop user stack ( decrementing) popud dst, src operation: dst ? src ir ? ir ? 1 this instruction is used for user-defined stacks in the register file. the contents of the register file location addressed by the user stack pointer are loaded into the destination. the user stack pointer is then decremented. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 92 r ir example: given: register 00h = 42h (user stack pointer register), register 42h = 6fh, and register 02h = 70h: popud 02h, @00h ? register 00h = 41h, register 02h = 6fh, register 42h = 6fh if general register 00h contains the value 42h and register 42h the value 6fh, the statement "popud 02h, @00h" loads the contents of register 42h into the destination register 02h. the user stack pointer is then decremented by one, leaving the value 41h.
s3c852b/P852B (preliminary spec) instruction set 6- 65 popui ? pop user stack (incrementing) popui dst, src operation: dst ? src ir ? ir + 1 the popui instruction is used for user-defined stacks in the register file. the contents of the register file location addressed by the user stack pointer are loaded into the destination. the user stack pointer is then incremented. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 93 r ir example: given: register 00h = 01h and register 01h = 70h: popui 02h, @00h ? register 0 0h = 02h, register 01h = 70h, register 02h = 70h if general register 00h contains the value 01h and register 01h the value 70h, the statement "popui 02h, @00h" loads the value 70h into the destination general register 02h. the user stack pointer (register 00h) is then incremented by one, changing its value from 01h to 02h.
instruction set s3c 852b/P852B (preliminary spec) 6- 66 push ? push to stack push src operation: sp ? sp ? 1 @sp ? src a push instruction decrements the stack pointer value and loads the contents of the sourc e (src) into the location addressed by the decremented stack pointer. the operation then adds the new value to the top of the stack. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc src 2 8 (internal clock) 70 r 8 (external clock) 8 (internal clock) 8 (external clock) 71 ir examples: given: register 40h = 4fh, register 4fh = 0aah, sph = 00h, and spl = 00h: push 40h ? register 40h = 4fh, stack register 0ffh = 4fh , sph = 0ffh, spl = 0ffh push @40h ? register 40h = 4fh, register 4fh = 0aah, stack register 0ffh = 0aah, sph = 0ffh, spl = 0ffh in the first example, if the stack pointer contains the value 0000h, and general register 40h the value 4fh, the statement "push 40h" decrements the stack pointer from 0000 to 0ffffh. it then loads the contents of register 40h into location 0ffffh and adds this new value to the top of the stack.
s3c852b/P852B (preliminary spec) instruction set 6- 67 pushud ? push user stack ( decrementing) pushud dst, src operation: ir ? ir ? 1 dst ? src this instruction is used to address user-defined stacks in the register file. pushud decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst src 3 8 82 ir r example: given: register 00h = 03h, register 01h = 05h, and register 02h = 1ah: pushud @00h, 01h ? register 00 h = 02h, register 01h = 05h, register 02h = 05h if the user stack pointer (register 00h, for example) contains the value 03h, the statement "pushud @00h, 01h" decrements the user stack pointer by one, leaving the value 02h. the 01h register value, 05h, is then loaded into the register addressed by the decremented user stack pointer.
instruction set s3c 852b/P852B (preliminary spec) 6- 68 pushui ? push user stack (incrementing) pushui dst, src operation: ir ? ir + 1 dst ? src this instruction is used for user-defined stacks in the register file. pushui increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst src 3 8 83 ir r example: given: register 00h = 03h, register 01h = 05h, and register 04h = 2ah: pushui @00h, 01h ? register 00h = 04h, register 01h = 05h, register 04h = 05h if the user stack pointer (register 00h , for example) contains the value 03h, the statement "pushui @00h, 01h" increments the user stack pointer by one, leaving the value 04h. the 01h register value, 05h, is then loaded into the location addressed by the incremented user stack pointer.
s3c852b/P852B (preliminary spec) instruction set 6- 69 rcf ? reset carry flag rcf rcf operation: c ? 0 the carry flag is cleared to logic zero, regardless of its previous value. flags: c: cleared to "0". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 cf example: given: c = "1" or "0": the instruction rcf clears the carry flag (c) to logic zero.
instruction set s3c 852b/P852B (preliminary spec) 6- 70 ret ? return ret operation: pc ? @sp sp ? sp + 2 the ret instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a call instruction. the contents of the location addressed by the stack pointer are popped into the program counter. the next statement that is executed is the one that is addressed by the new program counter value. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 8 (internal stack) af 10 (internal stack) example: given: sp = 00fch, (sp) = 101ah, and pc = 1234: ret ? pc = 101ah, sp = 00feh the statement "ret" pops the contents of stack pointer location 00fch (10h) into the high byte of the program counter. the stack pointer then pops the value in location 00feh (1ah) into the pc's low byte and the instruction at location 101ah is executed. the stack pointer now points to memory location 00feh.
s3c852b/P852B (preliminary spec) instruction set 6- 71 rl ? rotate left rl dst operation: c ? dst (7) dst (0) ? dst (7) dst (n + 1) ? dst (n), n = 0?6 the contents of the destination operand are rotated left one bit position. the initial value of bit 7 is moved to the bit zero (lsb) position and also replaces the carry flag. 7 0 c flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result b it 7 is set; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 90 r 4 91 ir examples: given: register 00h = 0aah, register 01h = 02h and register 02h = 17h: rl 00h ? register 00h = 55h, c = "1" rl @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h contains the value 0aah (10101010b), the statement "rl 00h" rotates the 0aah value left one bit position, leaving the new value 55h (01010101b) and setting the carry and overflow flags.
instruction set s3c 852b/P852B (preliminary spec) 6- 72 rlc ? rotate left through carry rlc dst operation: dst (0) ? c c ? dst (7) dst (n + 1) ? dst (n), n = 0?6 the contents of the destination operand with the carry flag are rotated left one bit position. the initial value of bit 7 replaces the carry flag (c); the initial value of the carry flag replaces bit zero. 7 0 c flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 10 r 4 11 ir examples: given: register 00h = 0aah, register 01h = 02h, and register 02h = 17h, c = "0": rlc 00h ? register 00h = 54h, c = "1" rlc @01h ? register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if general register 00h has the value 0aah (10101010b), the statement "rlc 00h" rotates 0aah one bit position to the left. the initial value of bit 7 sets the carry flag and the initial value of the c flag replaces bit zero of register 00h, leaving the value 55h (01010101b). the msb of register 00h resets the carry flag to "1" and sets the overflow flag.
s3c852b/P852B (preliminary spec) instruction set 6- 73 rr ? rotate right rr dst operation: c ? dst (0) dst (7) ? dst (0) dst (n) ? dst (n + 1), n = 0?6 the contents of the destination operand are rotated right one bit position. the initial value of bit zero (lsb) is moved to bit 7 (msb) and also replaces the carry flag (c). 7 0 c flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared othe rwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 e0 r 4 e1 ir examples: given: register 00h = 31h, register 01h = 02h, and register 02h = 17h: rr 00h ? register 00h = 98h, c = "1" rr @01h ? register 01h = 02h, register 02h = 8bh, c = "1" in the first example, if general register 00h contains the val ue 31h (00110001b), the statement "rr 00h" rotates this value one bit position to the right. the initial value of bit zero is moved to bit 7, leaving the new value 98h (10011000b) in the destination register. the initial bit zero also resets the c flag to "1" and the sign flag and overflow flag are also set to "1".
instruction set s3c 852b/P852B (preliminary spec) 6- 74 rrc ? rotate right through carry rrc dst operation: dst (7) ? c c ? dst (0) dst (n) ? dst (n + 1), n = 0?6 the contents of the destination operand and the carry fla g are rotated right one bit position. the initial value of bit zero (lsb) replaces the carry flag; the initial value of the carry flag replaces bit 7 (msb). 7 0 c flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0" cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. d: unaf fected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 c0 r 4 c1 ir examples: given: register 00h = 55h, register 01h = 02h, register 02h = 17h, and c = "0": rrc 00h ? register 00h = 2ah, c = "1" rrc @01h ? register 01h = 02h, register 02h = 0bh, c = "1" in the first example, if general register 00h contains the value 55h (01010101b), the statement "rrc 00h" rotates this value one bit position to the right. the initial value of bit zero ("1") replaces the carry flag and the initial value of the c flag ("1") replaces bit 7. this leaves the new value 2ah (00101010b) in destination register 00h. the sign flag and overflow flag are both cleared to "0".
s3c852b/P852B (preliminary spec) instruction set 6- 75 sb0 ? select bank 0 sb0 operation: bank ? 0 the sb0 instruction clears the bank address flag in the flags register (flags.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 4f example: the statement sb0 clears flags.0 to "0", selecting bank 0 register addressing.
instruction set s3c 852b/P852B (preliminary spec) 6- 76 sb1 ? select bank 1 sb1 operation: bank ? 1 the sb1 instruction sets the bank address flag in the flags register (flags.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (bank 1 is not implemented in some ks88-series microcontrollers.) flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 5f example: the statement sb1 sets flags.0 to "1", selecting bank 1 register addressing, if implemented.
s3c852b/P852B (preliminary spec) instruction set 6- 77 sbc ? subtract with carry sbc dst, src operation: dst ? dst ? src ? c the source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's-complement of the source operand to the destination operand. in multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. flags: c: set if a borrow occurred (src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 r r 6 35 r ir opc dst src 3 6 36 r im examples: given: r1 = 10h, r2 = 03h, c = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: sbc r1, r2 ? r1 = 0ch, r2 = 03h sbc r1, @r2 ? r1 = 05h, r2 = 03h, register 03h = 0ah sbc 01h, 02h ? register 01h = 1ch, register 02h = 03h sbc 01h, @02h ? register 01h = 15h, register 02h = 03h, register 03h = 0ah sbc 01h, #8ah ? register 01h = 95h; c, s, and v = "1" in the first example, if working register r1 contains the value 10h and register r2 the value 03h, the statement "sbc r1, r2" subtracts the source value (03h) and the c flag value ("1") from the destination (10h) and then stores the result (0ch) in register r1.
instruction set s3c 852b/P852B (preliminary spec) 6- 78 scf ? set carry flag scf operation: c ? 1 the carry flag (c) is set to logic one, regardless of its previous value. flags: c: set to "1". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 df example: the statement scf sets the carry flag to logic one.
s3c852b/P852B (preliminary spec) instruction set 6- 79 sra ? shift right arithmetic sra dst operation: dst (7) ? dst (7) c ? dst (0) dst (n) ? dst (n + 1), n = 0?6 an arithmetic shift-r ight of one bit position is performed on the destination operand. bit zero (the lsb) replaces the carry flag. the value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. 7 0 c 6 flags: c: set if the bit shifted from the lsb position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 d0 r 4 d1 ir examples: given: register 00h = 9ah, register 02h = 03h, register 03h = 0bch, and c = "1": sra 00h ? register 00h = 0cd, c = "0" sra @02h ? register 02h = 03h, register 03h = 0deh, c = "0" in the first example, if general register 00h contains the value 9ah (10011010b), the statement "sra 00h" shifts the bit values in register 00h right one bit position. bit zero ("0") clears the c flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). this leaves the value 0cdh (11001101b) in destination register 00h.
instruction set s3c 852b/P852B (preliminary spec) 6- 80 srp/srp0/srp1 ? set register pointer srp src srp0 src srp1 src operation: if src (1) = 1 and src (0) = 0 then: rp0 (3?7) ? src (3?7) if src (1) = 0 and src (0) = 1 then: rp1 (3?7) ? src (3?7) if src (1) = 0 and src (0) = 0 then: rp0 (4?7) ? src (4?7), rp0 (3) ? 0 rp1 (4?7) ? src (4?7), rp1 (3) ? 1 the source data bits one and zero (lsb) determine whether to write one or b oth of the register pointers, rp0 and rp1. bits 3?7 of the selected register pointer are written unless both register pointers are selected. rp0.3 is then cleared to logic zero and rp1.3 is set to logic one. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode src opc src 2 4 31 im examples: the statement srp #40h sets register pointer 0 (rp0) at location 0d6h to 40h and register pointer 1 (rp1) at location 0d7h to 48h. the statement "srp0 #50h" sets rp0 to 50h, and the statement "srp1 #68h" sets rp1 to 68h.
s3c852b/P852B (preliminary spec) instruction set 6- 81 stop ? stop operation stop operation: the stop instruction stops the both the cpu clock and system clock and causes the microcontroller to enter stop mode. during stop mode, the contents of on-chip cpu registers, peripheral registers, and i/o port control and data registers are retained. stop mode can be released by an external reset operation or by external interrupts. for the reset operation, the reset pin must be held to low level until the required oscillation stabilization interval has elapsed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 7f ? ? example: the statement stop halts all microcontroller operations.
instruction set s3c 852b/P852B (preliminary spec) 6- 82 sub ? subtract sub dst, src operation: dst ? dst ? src the source operand is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's complement of the source operand to the destination operand. flags: c: set if a "borrow" occurred; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four b its of the result; set otherwise indicating a "borrow". format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 r r 6 25 r ir opc dst src 3 6 26 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: sub r1, r2 ? r1 = 0fh, r2 = 03h sub r1, @r2 ? r1 = 08h, r2 = 03h sub 01h, 02h ? register 01h = 1eh, register 02h = 03h sub 01h , @02h ? register 01h = 17h, register 02h = 03h sub 01h, #90h ? register 01h = 91h; c, s, and v = "1" sub 01h, #65h ? register 01h = 0bch; c and s = "1", v = "0" in the first example, if working register r1 contains the value 12h and if register r2 contains the value 03h, the statement "sub r1, r2" subtracts the source value (03h) from the destination value (12h) and stores the result (0fh) in destination register r1.
s3c852b/P852B (preliminary spec) instruction set 6- 83 swap ? swap nibbles swap dst operation: dst (0 ? 3) ? dst (4 ? 7) the contents of the lower four bits and upper four bits of the destination operand are swapped. 7 0 4 3 flags: c: undefined. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 f0 r 4 f1 ir examples: given: register 00h = 3eh, register 02h = 03h, and register 03h = 0a4h: swap 00h ? register 00h = 0e3h swap @02h ? register 02h = 03h, register 03h = 4ah in the first example, if general register 00h contains the value 3eh (00111110b), the statement "swap 00h" swaps the lower and upper four bits (nibbles) in the 00h register, leaving the value 0e3h (11100011b).
instruction set s3c 852b/P852B (preliminary spec) 6- 84 tcm ? test complement under mask tcm dst, src operation: (not dst) and src this instruction tests selected bits in the destination operand for a logic one value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). the tcm statement complements the destination operand, which is then anded with the source mask. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 r r 6 65 r ir opc dst src 3 6 66 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 12h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tcm r0, r1 ? r0 = 0c7h, r1 = 02h, z = "1" tcm r0, @r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tcm 00h, 01h ? register 00h = 2bh, register 01h = 02h, z = "1" tcm 00h, @01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "1" tcm 00h, #34 ? register 00h = 2bh, z = "0" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tcm r0, r1" tests bit one in the destination register for a "1" value. because the mask value corresponds to the test bit, the z flag is set to logic one and can be tested to determine the result of the tcm operation.
s3c852b/P852B (preliminary spec) instruction set 6- 85 tm ? test under mask tm dst, src operation: dst and src this instruction tests selected bits in the destination operand for a logic zero value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is anded with the destination operand. the zero (z) flag can then be checked to determine the result. the destination and source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared other wise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 r r 6 75 r ir opc dst src 3 6 76 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tm r0, r1 ? r0 = 0c7h, r1 = 02h, z = "0" tm r0, @r1 ? r0 = 0c7h, r1 = 02h, register 02h = 23h, z = " 0" tm 00h, 01h ? register 00h = 2bh, register 01h = 02h, z = "0" tm 00h, @01h ? register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "0" tm 00h, #54h ? register 00h = 2bh, z = "1" in the first example, if working register r0 contains the value 0c7h (11000111b) and register r1 the value 02h (00000010b), the statement "tm r0, r1" tests bit one in the destination register for a "0" value. because the mask value does not match the test bit, the z flag is cleared to logic zero and can be tested to determine the result of the tm operation.
instruction set s3c 852b/P852B (preliminary spec) 6- 86 wfi ? wait for interrupt wfi operation: the cpu is effectively halted until an interrupt occurs, except that dma transfers can still take place during this wait state. the wfi status can be released by an internal interrupt, including a fast interrupt . flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4n 3f ( n = 1, 2, 3, ? ) example: the following sample program structure shows the sequence of operations that follow a "wfi" statement: main program ei wfi (next instruction) interrupt occurs interrupt service routine clear interrupt flag iret service routine completed (enable global interrupt) (wait for interrupt) . . . . . . . . .
s3c852b/P852B (preliminary spec) instruction set 6- 87 xor ? logical exclusive or xor dst, src operation: dst ? dst xor src the source operand is logically exclusive-ored with the destination operand and the result is stored in the destination. the exclusive-or operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 b2 r r 6 b3 r lr opc src dst 3 6 b4 r r 6 b5 r ir opc dst src 3 6 b6 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: xor r0, r1 ? r0 = 0c5h, r1 = 02h xor r0, @r1 ? r0 = 0e4h, r 1 = 02h, register 02h = 23h xor 00h, 01h ? register 00h = 29h, register 01h = 02h xor 00h, @01h ? register 00h = 08h, register 01h = 02h, register 02h = 23h xor 00h, #54h ? register 00h = 7fh in the first example, if working register r0 contains the value 0c7h and if register r1 contains the value 02h, the statement "xor r0, r1" logically exclusive-ors the r1 value with the r0 value and stores the result (0c5h) in the destination register r0.
instruction set s3c 852b/P852B (preliminary spec) 6- 88 notes
s3c852b/P852B (p reliminary s pec ) clock circuits 7- 1 7 clock circuits overview the s3c852b microcontroller has two oscillator circuits: a main system clock, and a subsystem clock circuit. the cpu and peripheral hardware operate on the system clock frequency supplied through these circuits. the maximum cpu clock frequency, is determined by clkcon register settings. system clock circuit the system clock circuit has the following components: ? external crystal source (main clock only), or an external clock ? programmable frequency divider for the cpu clock (fx divided by 1, 2, 8, or 16 or fxt) ? clock circuit control register, clkcon ? oscillator control register, osccon ? main clock control flag, mclksel ? phase locked loop for generating fx (3.579545 mhz) from fxt (32.768 khz) and generating fx*2 (7.159090 mhz) cpu clock notation in this document, the following notation is used for descriptions of the cpu clock: fx main clock fxt sub clock fxx selected system clock
clock circuits s3c8 52b/P852B (p reliminary s pec ) 7- 2 main oscillator circuits x in x out figure 7-1. crystal oscillator sub oscillator circuits xt in xt out 32.768 khz figure 7-2. crystal oscillator clock status during power-down modes stop mode affect the system clock as follows: ? in stop mode, the main oscillator is halted. stop mode is released, and the oscillator started, by a res et operation, by an external interrupt, or by a watch timer interrupt if sub clock is selected as watch timer clock source (when the fx is selected as system clock).
s3c852b/P852B (p reliminary s pec ) clock circuits 7- 3 1/1-1/4096 frequency dividing circuit main-system oscillator selector 1 f x fxt sub-system oscillator clkcon.7 osccon.0 osccon.3 osccon.2 1/1 1/16 1/2 1/8 selector 2 stop osc clkcon.4-.3 watch timer (fxt) adc sio basic timer watch timer (fxx/128) timer/counters int int cpu clock figure 7-3. system clock circuit diagram
clock circuits s3c8 52b/P852B (p reliminary s pec ) 7- 4 system clock control register (clkcon) the system clock control register, clkcon, is located in set 1, address d4h. it is read/write addressable and has the following functions: ? oscillator irq wake-up function enable/disable ? oscillator frequency divide-by value clkcon register settings control whether or not an external interrupt can be used to trigger a stop mode release (this is called the ?irq wake-up? function). the irq ?wake-up? enable bit is clkcon.7. after a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the f x /16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can then increase the cpu clock speed to f x , f x /2, or f x /8 by setting the clkcon, and you can change system clock from main clock to sub clock by setting the osccon. for the s3c852b microcontroller, the clkcon.2?clkcon.0 system clock signature code can be any value (the ?101b? setting selects sub clock as system clock). the reset value for the clock signature code is ?000b?. system clock control register (clkcon) set 1, d4h, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not use for s3c852b (must keep always "0") divide-by selection bits for cpu clock frequency: 00 = f x /16 or fxt 01 = f x /8 or fxt 10 = f x /2 or fxt 11 = f x or fxt (n on-divided) oscillator irq wake-up enable bit: 0 = enable irq for main system oscillator wake-up function in power down mode 1 = disable irq for main system oscillator wake-up function in power down mode not use for s3c852b (must keep always "0") figure 7-4. system clock control register (clkcon)
s3c852b/P852B (p reliminary s pec ) clock circuits 7- 5 oscillator control register (osccon) the oscillator control register, osccon, is located in set 1, address fah. it is read/write addressable and has the following functions: ? system clock selection ? main system oscillator control ? subsystem oscillator control osccon.0 register settings select main system clock or subsystem clock as system clock. after a reset, main system clock is selected for system clockn because the reset value of osccon.0 is ?0?. you can stop or run main system oscillator by setting osccon.3. you can stop or run subsystem oscillator by setting osccon.2. oscillator control register (osccon) set 1, bank 0, fah, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not use for s3c852b. main system oscillator control bit: 0 = main system oscillator run 1 = main system oscillator stop subsystem oscillator control bit: 0 = subsystem oscillator run 1 = subsystem oscillator stop not used for s3c852b. system clock selection bit: 0 = main system select 1 = subsystem oscillator select figure 7-5. oscillator control register (osccon)
clock circuits s3c8 52b/P852B (p reliminary s pec ) 7- 6 switching the cpu clock data loadings in the oscillator control register, osccon, determine whether a main or a sub clock is selected as the cpu clock, and also how this frequency is to be divided by setting clkcon. this makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies. osccon.0 select the main clock ( fx) or the sub clock ( fxt) for the cpu clock. osccon .3 start or stop main clock oscillation, and osccon.2 start or stop subsystem clock oscillation. clkcon.4?.3 control the frequency divider circuit, and divide the selected fx clock by 1, 2, 8, 16, or fxt clock by 1. for example, you are using the default cpu clock (normal operating mode and a main clock of fx/16 and you want to switch from the fx clock to a sub clock and to stop the main clock. to do this, you need to set osccon.0 to ?1? and osccon.3 to ?1? simultaneously. this switches the clock from fx to fxt and stops main clock oscillation. the following steps must be taken to switch from a sub clock to the main clock: first, set osccon.3 to ?0? to enable main system clock oscillation. then, after a certain number of machine cycles has elapsed, select the main clock by setting osccon.0 to ?0?. main clock ( fx) can be double input crystal when the mclksel is setting to ?1?. f f programming tip ? switching the cpu clock 1. this example shows how to change from the main clock to the sub clock: ma2sub ld osccon,#01h ; switches to the sub clock ; stop the main clock oscillation ret 2. this example shows how to change from su b clock to main clock: sub2ma and osccon,#07h ; start the main clock oscillation call dly16 ; delay 16 ms and osccon,#06h ; switch to the main clock ret dly16 srp #0c0h ld r0,#20h del nop djnz r0,del ret
s3c852b/P852B (p reliminary s pec ) clock circuits 7- 7 stop control register (stpcon) the stop control register, stpcon, is located in set 1, address fbh. it is read/write addressable and has the following functions: ? enable/disable stop instruction after a reset, the stop instruction is disabled, because the value of stpcon is ?00000000b?. if necessary, you can use the stop instruction by setting the value of stpcon to ?10100101b?. stop control register (stpcon) set 1, bank 0, fbh, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb stop control bits: 00000000 = disable stop instruction 10100101 = enable stop instruction figure 7-6. stop control register (stpcon)
clock circuits s3c8 52b/P852B (p reliminary s pec ) 7- 8 phase locked loop (pll) main clock generation the pll is able to generate main clock (fx = 3.579545mhz) from sub clock (fxt). in this case crystal oscillator for xin and xout is removed. to enable the function generating main clock, connect cksel (pin 71) to vdd and pllc (pin72) to gnd through a capacitor (0.1uf). in stop mode, the pll function also stopped as main clock oscillator doubling main clock frequency pll is able to double the main clock frequency (fx) to (fx*2 = 7.159090mhz) for cpu clock. to enable the function, set the msclk bit (cont2.7) of cont2 (95h, page 8, refer to p14-19 & p14-27). in this case the frequency for cpu clock will be doubled, but the frequency of the clock for cid block wouldn't be changed and remains at 3.579545mhz. operating voltage of the pll is from 4.5v to 5.5v.
s3c852b/P852B (p reliminary s pec ) reset reset and power-down 8- 1 8 reset reset and power-down system reset overview during a power-on reset, the voltage at v dd goes to high level and the reset pin is forced to low level. the reset signal is input through a schmitt trigger circuit where it is then synchronized with the cpu clock. this procedure brings s3c852b/P852B into a known operating status. to allow time for internal cpu clock oscillation to stabilize, the reset pin must be held to low level for a minimum time interval after the power supply comes within tolerance. the minimum required oscillation stabilization time for a reset operation is 1 millisecond. whenever a reset occurs during normal operation (that is, when both v dd and reset are high level), the reset pin is forced low and the reset operation starts. all system and peripheral control registers are then reset to their default hardware values (see tables 8-1, 8-2, and 8-3). in summary, the following sequence of events occurs during a reset operation: ? all interrupts are disabled. ? the watchdog function (basic timer) is enabled. ? ports 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10 are set to schmitt trigger input mode and all pull-up resistors are disabled for the i/o port pin circuits. ? per ipheral control and data registers are disabled and reset to their default hardware values. ? the program counter (pc) is loaded with the program reset address in the rom, 0100h. ? when the programmed oscillation stabilization time interval has elapsed, the instruction stored in rom location 0100h (and 0101h) is fetched and executed. ? extbus register is set to 00h, it can affect external interface output while ea pin is low.
reset reset and power-down s3c85 2b/P852B (p reliminary s pec ) 8- 2 normal mode reset operation in normal (masked rom) mode, the ea pin is tied to v ss . a reset enables access to the 64 -kbyte on-chip rom. (the external interface is not automatically configured). rom-less mode reset operation to configure s3c852b/P852B as a rom-less device, you must apply a constant 5 v current to the ea pin. assuming the ea pin is held to high level (5 v) when a reset occurs, rom-less mode is entered and the external interface is configured automatically. note to program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010b' to the upper nibble of btcon.
s3c852b/P852B (p reliminary s pec ) reset reset and power-down 8- 3 hardware reset reset values tables 8-1, 8-2, and 8-3 list the reset values for cpu and system registers, peripheral control registers, and peripheral data registers following a reset operation. the following notation is used to represent reset values: ? a "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. ? an 'x' means that the bit value is undefined after a reset. ? a dash ( ? ) means that the bit is either not used or not mapped. table 8-1. s3c852b/P852B set 1 register and values after reset reset (masked rom mode) register name mnemonic address bit values after reset reset (ea pin is low) dec hex 7 6 5 4 3 2 1 0 timer 0 counter t0cnt 208 d0h 0 0 0 0 0 0 0 0 timer 0 data register t0data 209 d1h 1 1 1 1 1 1 1 1 timer 0 control register t0con 210 d2h 0 0 0 0 0 0 0 0 basic timer control register btcon 211 d3h 0 0 0 0 0 0 0 0 clock control register clkcon 212 d4h 0 0 0 0 0 0 0 0 system flags register flags 213 d5h x x x x x x 0 0 register pointer 0 rp0 214 d6h 1 1 0 0 0 ? ? ? register pointer 1 rp1 215 d7h 1 1 0 0 1 ? ? ? stack pointer (high byte) sph 216 d8h x x x x x x x x stack pointer (low byte) spl 217 d9h x x x x x x x x instruction pointer (high byte) iph 218 dah x x x x x x x x instruction pointer (low byte) ipl 219 dbh x x x x x x x x interrupt request register irq 220 dch 0 0 0 0 0 0 0 0 interrupt mask register imr 221 ddh x x x x x x x x system mode register sym 222 deh 0 ? ? x x x 0 0 register page pointer pp 223 dfh 0 0 0 0 0 0 0 0
reset reset and power-down s3c85 2b/P852B (p reliminary s pec ) 8- 4 table 8-2. s3c852b/P852B set 1, bank 0 register and values after reset reset (masked rom mode) register name mnemonic address bit values after reset reset (ea pin is low) dec hex 7 6 5 4 3 2 1 0 port 0 data register p0 224 e0h 0 0 0 0 0 0 0 0 port 1 data register p1 225 e1h 0 0 0 0 0 0 0 0 port 2 data register p2 226 e2h 0 0 0 0 0 0 0 0 port 3 data register p3 227 e3h 0 0 0 0 0 0 0 0 port 4 data register p4 228 e4h 0 0 0 0 0 0 0 0 port 5 data register p5 229 e5h 0 0 0 0 0 0 0 0 port 6 data register p6 230 e6h 0 0 0 0 0 0 0 0 port 0 interrupt control register p0int 231 e7h 0 0 0 0 0 0 0 0 port 0 interrupt pending register p0pnd 232 e8h 0 0 0 0 0 0 0 0 port 0 interrupt state register p0sta 233 e9h 0 0 0 0 0 0 0 0 port 0 control register (high byte) p0conh 234 eah 0 0 0 0 0 0 0 0 port 0 control register (low byte) p0conl 135 ebh 0 0 0 0 0 0 0 0 port 1 control register (high byte) p1conh 236 ech 0 0 0 0 0 0 0 0 port 1 control register (low byte) p1conl 237 edh 0 0 0 0 0 0 0 0 port 1 function select register p1afs 238 eeh 0 0 0 0 0 0 0 0 port 2 function select register p2afs 240 f0h ? ? ? ? 0 0 0 0 port 3 control register p3con 241 f1h 0 0 0 0 0 0 0 0 port 3 function select register p3afs 242 f2h ? ? ? ? 0 0 0 0 port 4 control register p4con 243 f3h 0 0 0 0 0 0 0 0 port 5 control register p5con 244 f4h 0 0 0 0 0 0 0 0 port 6 control register p6con 245 f5h 0 0 0 0 0 0 0 0 clock output mode register clkmod 248 f8h ? ? ? ? ? 0 0 0 interrupt pending register intpnd 249 f9h ? ? ? ? ? 0 0 0 oscillator control register osccon 250 fah ? ? ? ? 0 0 ? 0 stop control register stpcon 251 fbh 0 0 0 0 0 0 0 0 basic timer counter btcnt 253 fdh x x x x x x x x external memory timing register emt 254 feh ? 1 1 1 1 1 0 ? interrupt priority register ipr 255 ffh x x x x x x x x
s3c852b/P852B (p reliminary s pec ) reset reset and power-down 8- 5 table 8-3. s3c852b/P852B set 1, bank 1 register values after reset reset (masked rom mode) register name mnemonic address bit values after reset reset (ea pin is low) dec hex 7 6 5 4 3 2 1 0 timer a counter tacnt 224 e0h 0 0 0 0 0 0 0 0 timer b counter tbcnt 225 e1h 0 0 0 0 0 0 0 0 timer a data register tadata 226 e2h 1 1 1 1 1 1 1 1 timer b data register tbdata 227 e3h 1 1 1 1 1 1 1 1 timer a control register tacon 228 e4h 0 0 0 0 0 0 0 0 timer b control register tbcon 229 e5h 0 0 0 0 0 0 0 0 watch timer control register wtcon 230 e6h 0 0 0 0 0 0 0 0 sio data register siodata 234 eah 1 1 1 1 1 1 1 1 sio control register siocon 235 ebh 0 0 0 0 0 0 0 0 sio pre-scaler register siops 236 ech 0 0 0 0 0 0 0 0 port 7 data register p7 237 edh 0 0 0 0 0 0 0 0 a/d data register(high byte) addatah 242 f2h x x x x x x x x a/d data register(low byte) addatal 243 f3h ? ? ? ? ? ? x x a/d control register adcon 244 f4h 0 0 0 0 0 0 0 0 port 8 data register p8 245 f5h 0 0 0 0 0 0 0 0 port 9 data register p9 246 f6h 0 0 0 0 0 0 0 0 port 10 data register p10 247 f7h 0 0 0 0 0 0 0 0 port 7 control register (high byte) p7conh 248 f8h 0 0 0 0 0 0 0 0 port 7 control register (low byte) p7conl 249 f9h 0 0 0 0 0 0 0 0 port 8 control register (high byte) p8conh 250 fah 0 0 0 0 0 0 0 0 port 8 control register (low byte) p8conl 251 fbh 0 0 0 0 0 0 0 0 port 9 control register (high byte) p9conh 252 fch 0 0 0 0 0 0 0 0 port 9 control register (low byte) p9conl 253 fdh 0 0 0 0 0 0 0 0 port 10 control register (high byte) p10conh 254 feh 0 0 0 0 0 0 0 0 port 10 control register (low byte) p10conl 255 ffh 0 0 0 0 0 0 0 0
reset reset and power-down s3c85 2b/P852B (p reliminary s pec ) 8- 6 power-down modes stop mode stop mode is invoked by the instruction stop. in stop mode, the operation of the cpu and main oscillator is halted. all peripherals which the main oscillator is selected as a clock source stop also because main oscillator stops. but, the watch timer will not halted in stop mode if the sub clock is selected as watch timer clock source. the data stored in the internal register file are retained in stop mode. stop mode can be released in one of three ways: by a system reset, by an internal watch timer interrupt (when sub clock is selected as clock source of watch timer), or by an external interrupt. example: stop nop nop nop notes 1. do not use stop mode if you are using an external clock source because x in input must be restricted internally to v ss to reduce current leakage. 2. in application programs, a stop instruction must be immediately followed by at least three nop instructions. this ensures an adequate time interval for the clock to stabilize before the next instruction is executed. if three or more nop instructions are not used after stop instruction, leakage current could be flown because of the floating state in the internal bus. using reset to release stop mode stop mode is released when the reset signal goes active (low level): all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. when the programmed oscillation stabilization interval has elapsed, the cpu starts the system initialization routine by fetching the program instruction stored in rom location 0100h. using an external interrupt to release stop mode external interrupts can be used to release stop mode. for the s3c852b microcontroller, we recommend using the int0?int7 interrupt, p0.0?p0.7. using an internal interrupt to release stop mode an internal interrupt, watch timer, can be used to release stop mode because the watch timer operates in stop mode if the clock source of watch timer is sub clock. if system clock is sub clock, you can't use any interrupts to release stop mode. please note the following conditions for stop mode release: ? if you release stop mode using an internal or external interrupt, the current values in system and peripheral control registers are unchanged. ? if you use an internal or external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. to do this, you must make the appropriate control and clock settings before entering stop mode. ? if you use an interrupt to release stop mode, the bit-pair setting for clkcon.4/clkcon.3 remains unchanged and the currently selected clock value is used. ? the internal or external interrupt is serviced when the stop mode release occurs. following the iret from the service routine, the instruction immediately following the one that initiated stop mode is executed.
s3c852b/P852B (p reliminary s pec ) reset reset and power-down 8- 7 idle mode idle mode is invoked by the instruction idl ( opcode 6fh). in idle mode, cpu operations are halted while some peripherals remain active. during idle mode, the internal clock signal is gated away from the cpu and from all but the following peripherals, which remain active : ? interrupt logic ? basic timer ? timer 0 ? timer 1 (timer a and b) ? watch timer i/o port pins retain the mode (input or output) they had at the time idle mode was entered. external interface pins are halted by high or low level, in the idle mode. idle mode release you can release idle mode in one of two ways: 1. execute a reset. all system and peripheral control registers are reset to their default values and the contents of all data registers are retained. the reset automatically selects the slowest clock (1/16) because of the hardware reset value for the clkcon register. if all external interrupts are masked in the imr register, a reset is the only way you can release idle mode. 2. activate any enabled interrupt ? internal or external. when you use an interrupt to release idle mode, the 2-bit clkcon.4/clkcon.3 value remains unchanged, and the currently selected clock value is used. the interrupt is then serviced. when the return-from-interrupt condition (iret) occurs, the instruction immediately following the one which initiated idle mode is executed.
reset reset and power-down s3c85 2b/P852B (p reliminary s pec ) 8- 8 f f programming tip ? sample s3c852b initialization routine the following sample program suggests initialization settings for the s3c852b address space, interrupt vectors, and peripheral functions: ; << register file reference >> .include ?c:\smds2p\include\reg\s3c852b.reg? ; << user equation definition >> .include ?c:\eq u.tbl? ; << interrupt vector addresses >> .org 00d0h .dw ext00_int ; irq6: edge triggered ext. int. .dw ext01_int ; irq6 .dw ext02_int ; irq6 .dw ext03_int ; irq6 ; 00d8h?00e3h: reserved .org 00e4h .dw ext04_int ; irq7: edge triggered ext. int. .dw ext05_int ; irq7 .dw ext06_int ; irq7 .dw ext07_int ; irq7 .org 00f0h .dw serial_r_t ; irq4 serial data receive/transmit interrupt .org 00f2h .dw wt ; irq3 watch timer overflow interrupt .org 00f4h .dw ta_match ; irq1 timer a match interrupt .dw tb_overflow ; irq1 timer b overflow interrupt .dw tb_match ; irq1 timer b match interrupt .org 00fah .dw t0_overflow ; irq0 timer 0 overflow interrupt .dw t0_m_c ; irq0 timer 0 match/capture interrupt ; 00feh?00ffh: reserved
s3c852b/P852B (p reliminary s pec ) reset reset and power-down 8- 9 f f programming tip ? sample s3c852b initialization routine (continued) ; << reset vector >> .org 0100h jp t, initial ? ? ? ; << system and peripheral initialization >> .org 02 00h initial: di ; ld sym,#00000000b ; fast, global interrupt disable ld emt,#00000000b ; 'no wait' and internal stack area select ld sph,#00h ; stack pointer (high byte) to zero ld spl,#0ffh ; stack pointer (low byte) to zero ld osccon,#00h ; select main clock as system clock ld clkcon,#10h ; f osc /2 is selected for cpu clock ; ld ipr,#16h ; interrupt priorities ; irq3 > 4 > 0 > 1 > 5 > 6 > 7 ld imr,#10001001b ; irq levels 0, 3, and 7 enable ; level 0 = timer 0 interrupt ; level 3 = watch timer interrupt ; level 7 = external interrupt
reset reset and power-down s3c85 2b/P852B (p reliminary s pec ) 8- 10 f f programming tip ? sample s3c852b initialization routine (continued) ini_peri_set: ; ld p0conh,#55h ; input, schmitt trigger, pull-up resistor enabled ld p0conl,#55h ld p0sta, #00h ; select falling edge interrupt detection ld p0pnd,#00h ; clear external interrupt pending bits ld p0int, #0ffh ; all external interrupt enable ; ld p1afs,#00h ; select normal i/o port 1 ld p1conh,#0aah ; output, push-pull ld p1conl,#0aah ; ld p2con,#0aah ; output, push-pull ; ld p3afs, #00h ; select normal i/o port 3 ld p3con,#0aah ; output, push-pull
s3c852b/P852B (p reliminary s pec ) reset reset and power-down 8- 11 f f programming tip ? sample s3c852b initialization routine (continued) ; ld p4con,#22h ; output, push-pull ; ld p5con,#22h ; output, push-pull ; < port 6 setting> ld p6con,#22h ; output, push-pull ; ld p7conh,#0aah ; output, push-pull ld p7conl,#0aah ; ld p8conh,#0aah ; output, push-pull ld p8conl,#0aah ; ld p9conh,#0aah ; output, push-pull ld p9conl,#0aah ; ld p10conh,#0aah ; output, push-pull ld p10conl,#0aah ; ld t0data,#08h ; timer a clock source clock divided by 9 ld t0con,#10001100b ; select fxx/64 as timer 0 clock source ; enable overflow interrup t ; ; disabled sb1 ld tacon,#00h ; ; disabled ld tbcon,#00h
reset reset and power-down s3c85 2b/P852B (p reliminary s pec ) 8- 12 f f programming tip ? sample s3c852b initialization routine (continued) ; ; disable ld siocon,#00h ; << register initialization >> sb0 srp #0c0h ; ld r0,#0ffh ramclr: clr @r0 djnz r0,ramclr ; ? ? ? ei ; must be executed in this position ; before external interrupt is executed ; << main loop >> main: no p ; start main loop ld btcon,#03h ; enable watchdog timer, clear btcnt, and ; basic timer clock input divider. ; ? ? ? call key_scan ? ? ? ? ? ? call job ? ? ? jp t,main
s3c852b/P852B (p reliminary s pec ) reset reset and power-down 8- 13 f f programming tip ? sample s3c852b initialization routine (continued) ; key_scan: nop ? ? ? ret ; job: nop ? ? ? ret ; << interrupt service routine >> t0_overflow:push rp0 ; irq0 push rp1 srp #t0_reg ; example: t0_reg = 00h ? ? ? and intpnd,#11111110b ; clear pending bi t (omissible) pop rp1 pop rp0 iret t0_m_c: and t0con,#11111110b ; clear pending bit, irq0 iret ta_match: and tacon,#11111110b ; clear pending bit, irq1 iret tb_overflow: and intpnd,#11111101b ; clear pending bit (omissible), irq1 iret tb_match: and intpnd,#11111011b ; clear pending bit, irq1 iret wt: and wtcon,#11111110b ; clear pending bit, irq3 iret
reset reset and power-down s3c85 2b/P852B (p reliminary s pec ) 8- 14 f f programming tip ? sample s3c852b initialization routine (concluded) ; << other interrupt vectors >> serial_r_t: and siocon,#11111110h ; clear pending bit, irq4 iret ext00_int: ld p0pnd,#11111110b ; clear pending bit, irq6 ? ? iret ext01_int: ld p0pnd,#11111101b ; clear pending bit, irq6 ? ? iret ext02_int: ld p0pnd,#11111011b ; clear pending bit, irq6 ? ? iret ext03_int: ld p0pnd,#11110111b ; clear pending bit, irq6 ? ? iret ext04_int: ld p0pnd,#11101111b ; cl ear pending bit, irq7 ? ? iret ext05_int: ld p0pnd,#11011111b ; clear pending bit, irq7 ? ? iret ext06_int: ld p0pnd,#10111111b ; clear pending bit, irq7 ? ? iret ext07_int: ld p0pnd,#01111111b ; clear pending bit, irq7 ? ? iret end note: when clearing a interrupt pending bit by software, using ld instruction is recommended to prevent malfunction of interrupt operation.
s3c852b/P852B (p reliminary s pec ) i/o ports 9- 1 9 i/o ports overview the s3c852b/P852B microcontrollers have p0?p10 i/o ports. p2 and p3 are 4-bit ports, the others are 8-bit ports. so, this gives a total of 80 i/o pins. each port can be flexibly configured to meet application design requirements. the cpu accesses ports by directly writing or reading port registers. no special i/o instructions are required. all ports of the s3c852b/P852B can be configured to input or output mode and p3?p6 are sharing with external interface, a0?a15, d0?d7, pm , dm , rd , wr . table 9-1 gives you a general overview of s3c852b i/o port functions.
i/o ports s3c852b/p 852b (p reliminary s pec ) 9- 2 table 9-1. s3c852b port configuration overview port configuration options 0 8-bit general-purpose i/o port; schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output. p0.1, p0.3, p0.5 and p0.6 can be used as alternative function (buz, t0, ta, tb). all p0 pin circuits have interrupt enable/disable (p0int), pending control(p0pnd), and rising/falling edge control (p0sta). 1 8-bit general-purpose i/o port; schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output, open-drain output. all p1 pin circuits have alternative function control(p1afs), the alternative functions of p1.0?p1.3 are the analog input function(adc0? adc3). 2 4-bit general-purpose i/o port; schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output, open-drain output. 3 4-bit general-purpose i/o port; schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output, open-drain output. all p3 pin circuits have alternative function control (p2afs), and the alternative functions of p3.0?p3.3 are the external memory interface function(pm, dm, rd, wr). 4 8-bit general-purpose i/o port; schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output, open-drain output. all p4 pin circuits can be used as alternative function for external memory interface function (d0?d7). 5 8-bit general-purpose i/o port; schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output, open-drain output. all p5 pin circuits can be used as alternative function for external memory interface function (a0?a7). 6 8-bit general-purpose i/o port; schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output, open-drain output. all p6 pin circuits can be used as alternative function for external memory interface function (a8?a15). 7 8-bit general-purpose i/o port; schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output, open-drain output. 8 8-bit general-purpose i/o port; schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output, open-drain output. 9 8-bit general-purpose i/o port; schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output, open-drain output. 10 8-bit general-purpose i/o port; schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output, open-drain output.
s3c852b/P852B (p reliminary s pec ) i/o ports 9- 3 port data registers table 9-2 gives you an overview of the register locations of all seven s3c852b i/o port data registers. data registers for ports 0 to 10 have the general format shown in figure 9-1. table 9-2. port data register summary register name mnemonic decimal hex location r/w port 0 data register p0 224 e0h set 1 r/w port 1 data register p1 225 e1h set 1 r/w port 2 data register p2 226 e2h set 1 r/w port 3 data register p3 227 e3h set 1 r/w port 4 data register p4 228 e4h set 1 r/w port 5 data register p5 229 e5h set 1 r/w port 6 data register p6 230 e6h set 1 r/w port 7 data register p7 237 edh set 1 r/w port 8 data register p8 245 f5h set 1 r/w port 9 data register p9 246 f6h set 1 r/w port 10 data register p10 247 f7h set 1 r/w s3c852b i/o port data register format (n = 0-6) .7 .6 .5 .4 .3 .2 .1 .0 msb lsb note: p2 and p3 have the only pn.0-pn.3 pn.7 pn.6 pn.5 pn.4 pn.3 pn.2 pn.1 pn.0 figure 9-1. s3c852b i/o port data register format
i/o ports s3c852b/p 852b (p reliminary s pec ) 9- 4 port 0 port 0 is an 8-bit i/o port with individually configurable pins. port 0 can serve either as a general-purpose 8-bit i/o port, alternative functions (buz for buzzer signal output, t0 for timer 0 output, ta for timer 1/a output and tb for timer b output), or its pins can be configured individually as external interrupt inputs. all inputs are schmitt triggered. port 0 is accessed directly by writing or reading the port 0 data register, p0 (r224, e0h) in set 1. port 0 control registers (p0conh, p0conl) the direction of each port pin is configured by bit-pair settings in two control registers: p0conh (high byte, eah, set 1) and p0conl (low byte, ebh, set 1). p0conh controls pins p0.4?p0.7 (pins 32?35) and p0conl controls pins p0.0?p0.3 (pins 28?31). both registers are read-write addressable using 8-bit instructions. when select alternative function by setting bit-pair to ?11?(p0.1, p0.3, p0.5, p0.6), p0.1, p0.3, p0.5, p0.6 can be automatically configured respectively, as buz, timer 0, timer 1/a and timer b output. there are two input mode and one output mode: schmitt trigger input, schmitt trigger input with pull-up resistor and push-pull output. a reset clears all p0conh and p0conl bits to logic zero. this configures port 0 pins to schmitt trigger input. port 0 interrupt enable and pending registers (p0int, p0pnd) to process external interrupts, two additional control registers are provided: the port 0 interrupt enable register, p0int (r231, e7h, set 1) and the port 0 interrupt pending register, p0pnd (r232, e8h, set 1). by setting bits in the port 0 interrupt enable register p0int to "1", you can use specific port 0 pins to generate interrupt requests when specific signal edges are detected. the interrupt names int0?int7 correspond to pins p0.0?p0.7. after a reset, p0int bits are cleared to ?00h?, disabling all external interrupts. the port 0 interrupt pending register p0pnd lets you check for interrupt pending conditions and clear the pending condition when the interrupt request has been serviced. incoming interrupt requests are detected by polling the p0pnd bit values. when the interrupt enable bit of any port 0 pin is set to "1", a rising or falling signal edge at that pin generates an interrupt request. (remember that the port 0 interrupt pins must first be configured by setting them to input mode in the corresponding p0conh or p0conl register.) the corresponding p0pnd bit is then set to "1" and the irq pulse goes high to signal the cpu that an interrupt request is waiting. when a port 0 interrupt request has been serviced, the application program must clear the appropriate interrupt pending register bit by writing a "0" to the correct pending bit in the p0pnd register. please note that writing a "0" value has no effect. port 0 interrupt state register (p0sta) p0 interrupt can be generated in falling edge or rising edge, depending on the value of the p0 interrupt state register (r233, e9h, set 1) p0sta. if the value is set to "1", p0 interrupt is generated in rising edge. if the value is set to "0", p0 interrupt is generated in falling edge.
s3c852b/P852B (p reliminary s pec ) i/o ports 9- 5 port 0 control register, high byte (p0conh) eah, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0.7/int7 p0conh bit-pair pin configuration settings: 00 01 10 11 input, schmitt trigger (t1ck) input, schmitt trigger, pull-up resistor (t1ck) output, push-pull select alternative function at p0.5 and p0.6 p0.6/int6/tb p0.5/int5/ta p0.4/int4/t1ck figure 9-2. port 0 control register (p0conh) port 0 control register, low byte (p0conl) ebh, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p0.3/int3/t0 p0conl bit-pair pin configuration settings: 00 01 10 11 input, schmitt trigger (t0ck, t0) input, schmitt trigger, pull-up resistor (t0ck, t0) output, push-pull select alternative function at p0.1 and p0.3 p0.2/int2/t0ck p0.1/int1/buz p0.0/int0 figure 9-3. port 0 control register (p0conl)
i/o ports s3c852b/p 852b (p reliminary s pec ) 9- 6 port 0 interrupt enable register (p0int) e7h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb port 0 interrupt control setting bits: 0 = disable interrupt at p0.n 1 = enable interrupt at p0.n p0.7/int7 p0.6/int6 p0.5/int5 p0.4/int4 p0.3/int3 p0.2/int2 p0.1/int1 p0.0/int0 figure 9-4. port 0 interrupt enable register (p0int) port 0 interrupt pending register (p0pnd) e8h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb port 0 interrupt repuest pending bits: 0 = interrupt request is not pending 1 = interrupt request is pending p0.7/int7 p0.6/int6 p0.5/int5 p0.4/int4 p0.3/int3 p0.2/int2 p0.1/int1 p0.0/int0 figure 9-5. port 0 interrupt pending register (p0pnd) port 0 interrupt state register (p0sta) e9h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb port 0 interrupt state setting bits: 0 = falling edge interrupt at p0.n 1 = rising edge interrupt at p0.n p0.7/int7 p0.6/int6 p0.5/int5 p0.4/int4 p0.3/int3 p0.2/int2 p0.1/int1 p0.0/int0 figure 9-6. port 0 interrupt state register (p0sta)
s3c852b/P852B (p reliminary s pec ) i/o ports 9- 7 port 1 port 1 is an 8-bit i/o port with individually configurable pins. port 1 can serve either as a general-purpose 8-bit i/o port, alternative functions (adc0?adc3) for analog to digital input. port 1 have the port 1 alternative function select register (p1afs) for selection alternative function of port 1. port 1 is accessed directly by writing or reading the port 1 data register, p1 (r225, e1h) in set 1. you can use port 1 for general i/o, or for the alternative functions by setting p1afs: port 1 control registers (p1conh, p1conl) the direction of each port pin is configured by bit-pair settings in two control registers: p1conh (high byte, ech, set 1) and p1conl (low byte, edh, set 1). p1conh controls pins p1.4?p1.7 (pins 40?43) and p1conl controls pins p1.0?p1.3 (pins 36?39). both registers are read-write addressable using 8-bit instructions. there are two input mode and two output mode: schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output and open-drain output. a reset clears all p1conh and p1conl bits to logic zero. this configures port 1 pins to schmitt trigger input. port 1 alternative function select register (p1afs) port 1 can be used either as a general-purpose 8-bit i/o port or alternative functions, depending on the value of the port 1 alternative function select register (r238, eeh, set 1) p1afs. if the p1afs is set to ?11111111b?, the corresponding pins are selected to alternative functions. if the p1afs is set to ?00000000b?, the corresponding pins are selected to general i/o ports. that is, ? p1.0?p1.3 can be configured as adc0?adc3 for analog to digital input by setting p1afs.0?p1afs.3 to "1". the special functions that you can program using the port 1 high byte control register must also be enabled in the associated peripheral. also, when using port 1 pins for functions other than general i/o, you must still set the corresponding port 1 control register value to configure each bit to input or output mode.
i/o ports s3c852b/p 852b (p reliminary s pec ) 9- 8 port 1 control register, high byte (p1conh) ech, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1.7 p1conh bit-pair pin configuration settings: 00 01 10 11 output, push-pull output, open-drain p1.6/ sck p1.5/so p1.4/si input, schmitt trigger, pull-up resistor input, schmitt trigger figure 9-7. port 1 high-byte control register (p1conh) port 1 control register, low byte (p1conl) edh, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p1.3/adc3 p1conl bit-pair pin configuration settings: 00 01 10 11 output, push-pull output, open-drain p1.2/adc2 p1.1/adc1 p1.0/adc0 input, schmitt trigger, pull-up resistor input, schmitt trigger figure 9-8. port 1 low-byte control register (p1conl)
s3c852b/P852B (p reliminary s pec ) i/o ports 9- 9 port 1 alternative function select register (p1afs) eeh, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb port 0 alternative function state settings: 0 = normal i/o port at p1.n 1 = select analog input function at p1.0-p1.3 p1.7 p1.6/ sck p1.5/so p1.4/si p1.3/adc3 p1.2/adc2 p1.1/adc1 p1.0/adc0 figure 9-9. port 1 alternative function select register (p1afs)
i/o ports s3c852b/p 852b (p reliminary s pec ) 9- 10 port 2 port 2 is an 4-bit i/o port with individually configurable pins. port 2 is accessed directly by writing or reading the port 2 data register, p2 (r226, e2h) in set 1. you can use port 2 for general i/o. port 2 control registers (p2con) the direction of each port pin is configured by bit-pair settings in port 2 control register: p2con (efh, set 1). p2con controls pins p2.0?p2.3 (pins 16?19). port 2 control registers is read-write addressable using 8-bit instructions. there are two input mode and two output mode: schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output and open-drain output. a reset clears all p2con bits to logic zero. this configures port 2 pins to schmitt trigger input. port 2 control register, low byte (p2con) efh, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p2.3 p2.2 p2.1 p2.0 p2con bit-pair pin configuration settings: 00 01 10 11 output, push-pull output, open-drain input, schmitt trigger, pull-up resistor input, schmitt trigger figure 9-10. port 2 control register (p2con)
s3c852b/P852B (p reliminary s pec ) i/o ports 9- 11 port 3 port 3 is an 4-bit i/o port with individually configurable pins. port 3 can serve either as a general-purpose 4-bit i/o port, alternative functions ( pm, dm, rd, wr for controlling external memory interface). port 3 have the port 3 alternative function select register(p3afs) for selection alternative function of port 3. port 3 is accessed directly by writing or reading the port 3 data register, p3 (r227, e3h) in set 1. you can use port 3 for general i/o, or for the alternative functions by setting p3afs. port 3 control registers (p3con) the direction of each port pin is configured by bit-pair settings in port 3 control register: p3con (f1h, set 1). p3con controls pins p3.0?p3.3 (pins 12?15). port 3 control registers is read-write addressable using 8-bit instructions. there are two input mode and two output mode: schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output and open-drain output. a reset clears all p3con bits to logic zero. this configures port 3 pins to schmitt trigger input. port 3 alternative function select register (p3afs) port 3 can be used either as a general-purpose 4-bit i/o port or alternative functions, depending on the value of the port 3 alternative function select register (r242, f2h, set 1) p3afs. if the p3afs is set to ?11111111b?, the corresponding pins are selected to alternative functions. if the p3afs is set to ?00000000b?, the corresponding pins are selected to general i/o ports. that is, ? p3.0?p3.3 can be configured as pm, dm, rd, wr for controlling external memory interface setting p3afs.0?f3afs.3 to "1".
i/o ports s3c852b/p 852b (p reliminary s pec ) 9- 12 port 3 control register, low byte (p3con) f1h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p3.3/ wr p3con bit-pair pin configuration settings: 00 01 10 11 output, push_pull output, open-drain input, schmitt trigger, pull_up input, schmitt trigger p3.2/ rd p3.1/ dm p3.0/ pm figure 9-11. port 3 control register (p3con) port 3 alternative functionselect register (p3afs) f2h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used for s3c852b port 3 alternative function state settings: 0 = normal i/o port at p3.n 1 = select alternative function at p3.n p3.3/ wr p3.2/ rd p3.1/ dm p3.0/ pm figure 9-12. port 3 alternative function select register (p3afs)
s3c852b/P852B (p reliminary s pec ) i/o ports 9- 13 port 4 port 4 can be configured on a nibble basis for general data input or output. port 4 can serve either as a general- purpose 8-bit i/o port or alternative functions (d0?d7 for the external peripheral interface). port 4 is accessed directly by writing or reading the port 4 data register, p4 (r228, e4h) in set 1. you can use port 4 for general i/o, or for the alternative functions by p4con setting "0100b" for each nibble configures the pins as external interface lines. the port 4 data register cannot be written, however, when port 4 bits are configured as data lines for the external interface: writes have no effect and reads only return the state of the pin. port 4 control registers (p4con) the direction of each port pin is configured by nibble settings in port 4 control register: p4con (f3h, set 1). p4con controls pins p4.0?p4.7 (pins 148?155). port 4 control registers is read-write addressable using 8-bit instructions. the p4con setting ?0100b? for each nibble configures the pins as external interface lines. bits 4?7 of p4con control the upper nibble pins, p4.4?p4.7, and bits 0?3 of p4con control the lower nibble pins, p4.0?p4.3. there are two input mode and two output mode: schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output and open-drain output. in normal operating mode a reset operation clears all p4con register values to "0" , this configures port 4 pins to schmitt trigger input. if you want to configure an external memory area, you can use routine to set the p4con value to ?01000100b?. this setting correctly configures data lines d0?d7. output, open-drain port 4 control register (p4con) f3h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb port 4 mode selection: input, schmitt trigger, pull_up resistor upper nibble port configuration input, schmitt trigger output, push_pull lower nibble port configuration 7(3) 6(2) 5(1) 4(0) 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 select external memory interface line at p4.n (d0-d7) figure 9-13. port 4 control register (p4con)
i/o ports s3c852b/p 852b (p reliminary s pec ) 9- 14 port 5 port 5 is basically identical to port 4, except that its alternate use is as the address lines (a0?a7) for the external interface. (port 4 can alternately be configures as the data lines d0?d7.) port 5 can be configured on a nibble basis for general data input or output. port 5 can serve either as a general- purpose 8-bit i/o port or alternative functions (a0?a7 for the external peripheral interface). port 5 is accessed directly by writing or reading the port 5 data register, p5 (r229, e5h) in set 1. you can use port 5 for general i/o, or for the alternative functions by p5con setting ?0100b? for each nibble configures the pins as external interface lines. the port 5 data register cannot be written, however, when port 5 bits are configured as address lines for the external interface: writes have no effect and reads only return the state of the pin. port 5 control registers (p5con) the direction of each port pin is configured by nibble settings in port 5 control register: p5con (f4h, set 1). p5con controls pins p5.0?p5.7 (pins 156?3). port 5 control registers is read-write addressable using 8-bit instructions. the p5con setting ?0100b? for each nibble configures the pins as external interface lines. bits 4?7 of p5con control the upper nibble pins, p5.4?p5.7, and bits 0?3 of p5con control the lower nibble pins, p5.0?p5.3. there are two input mode and two output mode: schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output and open-drain output. in normal operating mode a reset operation clears all p5con register values to "0" , this configures port 5 pins to schmitt trigger input. if you want to configure an external memory area, you can use routine to set the p5con value to ?01000100b?. this setting correctly configures address lines a0?a7. output, open-drain port 5 control register (p5con) f4h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb port 5 mode selection: input, schmitt trigger, pull_up resistor upper nibble port configuration input, schmitt trigger output, push_pull lower nibble port configuration 7(3) 6(2) 5(1) 4(0) 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 select external memory interface line at p5.n (a0-a7) figure 9-14. port 5 control register (p5con)
s3c852b/P852B (p reliminary s pec ) i/o ports 9- 15 port 6 port 6 is basically identical to port 4, except that its alternate use is as the address lines (a8? a15) for the external interface. (port 4 can alternately be configures as the data lines d0?d7.) port 6 can be configured on a nibble basis for general data input or output. port 6 can serve either as a general- purpose 8-bit i/o port or alternative functions (a8?a15 for the external peripheral interface). it is possible to configure the lower nibble as external interface address lines a8?a11, and to use the upper nibble pins for general i/o. port 6 is accessed directly by writing or reading the port 6 data register, p6 (r230, e6h) in set 1. you can use port 6 for general i/o, or for the alternative functions by p6con setting ?0100b? for each nibble configures the pins as external interface lines. the port 6 data register cannot be written, however, when port 6 bits are configured as address lines for the external interface: writes have no effect and reads only return the state of the pin. port 6 control registers (p6con) the direction of each port pin is configured by nibble settings in port 6 control register: p6con (f5h, set 1). p6con controls pins p6.0?p6.7 (pins 4?11). port 6 control registers is read-write addressable using 8-bit instructions. the p6con setting ?0100b? for each nibble configures the pins as external interface lines. bits 4?7 of p6con control the upper nibble pins, p6.4?p6.7, and bits 0?3 of p6con control the lower nibble pins, p6.0?p6.3. there are two input mode and two output mode: schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output and open-drain output. in normal operating mode a reset operation clears all p6con register values to "0" , this configures port 6 pins to schmitt trigger input. if you want to configure an external memory area, you can use routine to set the p6con value to ?01000100b?. this setting correctly configures address lines a8?a15. output, open-drain port 6 control register (p6con) f5h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb port 6 mode selection: input, schmitt trigger, pull_up resistor upper nibble port configuration input, schmitt trigger output, push_pull lower nibble port configuration 7(3) 6(2) 5(1) 4(0) 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 select external memory interface line at p6.n (a8-a15) figure 9-15. port 6 control register (p6con)
i/o ports s3c852b/p 852b (p reliminary s pec ) 9- 16 port 7 port 7 is an 8-bit i/o port with individually configurable pins. port 7 is accessed directly by writing or reading the port 7 data register, p7 (r237, edh) in set 1. you can use port 1 for general i/o. port 7 control registers (p7conh, p7conl) the direction of each port pin is configured by bit-pair settings in two control registers: p7conh (high byte, f8h, set 1) and p7conl (low byte, f9h, set 1). p7conh controls pins p7.4?p7.7 and p7conl controls pins p7.0? p7.3. both registers are read-write addressable using 8-bit instructions. there are two input mode and two output mode: schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output and open-drain output. a reset clears all p7conh and p7conl bits to logic zero. this configures port 7 pins to schmitt trigger input. port 7 control register, high byte (p7conh) f8h, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p7.7 p7conh bit-pair pin configuration settings: 00 01 10 11 output, push-pull output, open-drain p7.6 p7.5 p7.4 input, schmitt trigger, pull-up resistor input, schmitt trigger figure 9-16. port 7 high-byte control register (p7conh) port 7 control register, low byte (p7conl) f9h, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p7.3 p7conl bit-pair pin configuration settings: 00 01 10 11 output, push-pull output, open-drain p7.2 p7.1 p7.0 input, schmitt trigger, pull-up resistor input, schmitt trigger figure 9-17. port 7 low-byte control register (p7conl)
s3c852b/P852B (p reliminary s pec ) i/o ports 9- 17 port 8 port 8 is an 8-bit i/o port with individually configurable pins. port 8 is accessed directly by writing or reading the port 8 data register, p8 (r245, f5h) in set 1. you can use port 8 for general i/o. port 8 control registers (p8conh, p8conl) the direction of each port pin is configured by bit-pair settings in two control registers: p8conh (high byte, fah, set 1) and p8conl (low byte, fbh, set 1). p8conh controls pins p8.4?p8.7 and p8conl controls pins p8.0? p8.3. both registers are read-write addressable using 8-bit instructions. there are two input mode and two output mode: schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output and open-drain output. a reset clears all p8conh and p8conl bits to logic zero. this configures port 8 pins to schmitt trigger input. port 8 control register, high byte (p8conh) fah, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p8.7 p8conh bit-pair pin configuration settings: 00 01 10 11 output, push-pull output, open-drain p8.6 p8.5 p8.4 input, schmitt trigger, pull-up resistor input, schmitt trigger figure 9-18. port 8 high-byte control register (p8conh) port 8 control register, low byte (p8conl) fbh, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p8.3 p8conl bit-pair pin configuration settings: 00 01 10 11 output, push-pull output, open-drain p8.2 p8.1 p8.0 input, schmitt trigger, pull-up resistor input, schmitt trigger figure 9-19. port 8 low-byte control register (p8conl)
i/o ports s3c852b/p 852b (p reliminary s pec ) 9- 18 port 9 port 9 is an 8-bit i/o port with individually configurable pins. port 9 is accessed directly by writing or reading the port 9 data register, p9 (r246, f6h) in set 1. you can use port 9 for general i/o. port 9 control registers (p9conh, p9conl) the direction of each port pin is configured by bit-pair settings in two control registers: p9conh (high byte, fch, set 1) and p9conl (low byte, fdh, set 1). p9conh controls pins p9.4?p9.7 and p9conl controls pins p9.0? p9.3. both registers are read-write addressable using 8-bit instructions. there are two input mode and two output mode: schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output and open-drain output. a reset clears all p9conh and p9conl bits to logic zero. this configures port 9 pins to schmitt trigger input. port 9 control register, high byte (p9conh) fch, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p9.7 p9conh bit-pair pin configuration settings: 00 01 10 11 output, push-pull output, open-drain p9.6 p9.5 p9.4 input, schmitt trigger, pull-up resistor input, schmitt trigger figure 9-20. port 9 high-byte control register (p9conh) port 9 control register, low byte (p9conl) fdh, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p9.3 p9conl bit-pair pin configuration settings: 00 01 10 11 output, push-pull output, open-drain p9.2 p9.1 p9.0 input, schmitt trigger, pull-up resistor input, schmitt trigger figure 9-21. port 9 low-byte control register (p9conl)
s3c852b/P852B (p reliminary s pec ) i/o ports 9- 19 port 10 port 10 is an 8-bit i/o port with individually configurable pins. port 10 is accessed directly by writing or reading the port 10 data register, p10 (r247, f7h) in set 1. you can use port 10 for general i/o. port 10 control registers (p10conh, p10conl) the direction of each port pin is configured by bit-pair settings in two control registers: p10conh (high byte, feh, set 1) and p10conl (low byte, ffh, set 1). p10conh controls pins p10.4?p10.7 and p10conl controls pins p10.0?p10.3. both registers are read-write addressable using 8-bit instructions. there are two input mode and two output mode: schmitt trigger input, schmitt trigger input with pull-up resistor, push-pull output and open-drain output. a reset clears all p10conh and p10conl bits to logic zero. this configures port 10 pins to schmitt trigger input. port 10 control register, high byte (p10conh) feh, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p10.7 p10conh bit-pair pin configuration settings: 00 01 10 11 output, push-pull output, open-drain p10.6 p10.5 p10.4 input, schmitt trigger, pull-up resistor input, schmitt trigger figure 9-22. port 10 high-byte control register (p10conh) port 10 control register, low byte (p10conl) ffh, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb p10.3 p10conl bit-pair pin configuration settings: 00 01 10 11 output, push-pull output, open-drain p10.2 p10.5 p10.0 input, schmitt trigger, pull-up resistor input, schmitt trigger figure 9-23. port 10 low-byte control register (p10conl)
i/o ports s3c852b/p 852b (p reliminary s pec ) 9- 20 notes
s3c852b/P852B (p reliminary s pec ) basic timer and timer 0 10- 1 10 basic timer and timer 0 module overview the s3c852b has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter. the 8 -bit timer/counter is called timer 0. basic timer (bt) you can use the basic timer (bt) in two different ways: ? as a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. ? to signal the end of the required oscillation stabilization interval after a reset or a stop mode release. the functional components of the basic timer block are: ? clock frequency divider (f xx divided by 4096, 1024, 128, or 16) with multiplexer ? 8-bit basic timer counter, btcnt (set 1, bank 0, fdh, read-only) ? basic timer control register, btcon (set 1, d3h, read/write)
basic timer and timer 0 s3c852b/p8 52b (p reliminary s pec ) 10- 2 basic timer control register (btcon) the basic timer control register, btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. it is located in set 1, address d3h, and is read/write addressable using register addressing mode. a reset clears btcon to ?00h?. this enables the watchdog function and selects a basic timer clock frequency of f xx /4096. to disable the watchdog function, you must write the signature code ?1010b? to the basic timer register control bits btcon.7?btcon.4. the 8-bit basic timer counter, btcnt (set 1, bank 0, fdh), can be cleared at any time during normal operation by writing a "1" to btcon.1. to clear the frequency dividers for both the basic timer input clock, you write a "1" to btcon.0. basic timer control register (btcon) d3h, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb divider clear bit for basic timer : 0 = no effect 1 = clear divider basic timer counter clear bit: 0 = no effect 1 = clear btcnt basic timer input clock selection bits: 00 = f xx /4096 01 = f xx /1024 10 = f xx /128 11 = f xx /16 watchdog function enable bits: 1010b other value = disable watchdog timer = enable watchdog timer figure 10-1. basic timer control register (btcon)
s3c852b/P852B (p reliminary s pec ) basic timer and timer 0 10- 3 basic timer function description watchdog timer function you can program the basic timer overflow signal (btovf) to generate a reset by setting btcon.7?btcon.4 to any value other than ?1010b?. (the ?1010b? value disables the watchdog function.) a reset clears btcon to ?00h?, automatically enabling the watchdog timer function. a reset also selects the cpu clock (as determined by the current clkcon register setting), divided by 4096, as the bt clock. a reset whenever a basic timer counter overflow occurs. during normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. to do this, the btcnt value must be cleared (by writing a "1" to btcon.1) at regular intervals. if a system malfunction occurs due to circuit noise or some other error condition, the bt counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. in other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, btcnt) is always broken by a btcnt clear instruction. if a malfunction does occur, a reset is triggered automatically. oscillation stabilization interval timer function you can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt. in stop mode, whenever a reset or an internal and an external interrupt occurs, the oscillator starts. the btcnt value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an internal and an external interrupt). when btcnt.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the cpu so that it can resume normal operation. in summary, the following events occur when stop mode is released: 1. during stop mode, a power-on reset or an internal and an external interrupt occurs to trigger the stop mode release and oscillation starts. 2. if a power-on reset occurred, the basic timer counter will increase at the rate of fx x /4096. if an internal and an external interrupt is used to release stop mode, the btcnt value increases at the rate of the preset clock source. 3. clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows. 4. when a btcnt.3 overflow occurs, normal cpu operation resumes.
basic timer and timer 0 s3c852b/p8 52b (p reliminary s pec ) 10- 4 note: during a power-on reset operation, the cpu is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). mux f xx /4096 div f xx /1024 f xx /128 f xx /16 f xx bits 3, 2 bit 0 basic timer control register (write '1010xxxxb' to disable) clear bit 1 reset or stop data bus 8-bit up counter (btcnt, read-only) start the cpu (note) ovf reset r figure 10-2. basic timer block diagram
s3c852b/P852B (p reliminary s pec ) basic timer and timer 0 10- 5 8-bit timer 0 timer 0 has three operating modes, one of which you select using the appropriate t0con setting: ? interval timer mode ? capture input mode with a rising or falling edge trigger at the p0.3 pin ? pwm mode timer 0 has the following functional components: ? clock frequency divider (fxx divided by 1024, 256, or 64) with multiplexer ? external clock input pin (p0.2, t0ck) ? 8-bit counter (t0cnt), 8-bit comparator, and 8-bit reference data register (t0data) ? i/o pins for capture input or match output (p0.3, t0) ? timer 0 overflow interrupt (irq0, vector fah) and match/capture interrupt (irq0, vector fch) generation ? timer 0 control register, t0con (set 1, d2h, rea d/write) timer 0 control register (t0con) you use the timer 0 control register, t0con, to ? select the timer 0 operating mode (interval timer, capture mode, or pwm mode) ? select the timer 0 input clock frequency ? clear the timer 0 counter, t0cnt ? enable the timer 0 overflow interrupt or timer 0 match/capture interrupt ? clear timer 0 match/capture interrupt pending conditions
basic timer and timer 0 s3c852b/p8 52b (p reliminary s pec ) 10- 6 t0con is located in set 1, at address d2h, and is read/write addressable using register addressing mode. a reset clears t0con to ?00h?. this sets timer 0 to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer 0 interrupts. you can clear the timer 0 counter at any time during normal operation by writing a "1" to t0con.3. the timer 0 overflow interrupt (t0ovf) is interrupt level irq0 and has the vector address fah. when a timer 0 overflow interrupt occurs and is serviced by the cpu, the pending condition is cleared automatically by hardware. to enable the timer 0 match/capture interrupt (irq0, vector fch), you must write t0con.1 to "1". to detect a match/capture interrupt pending condition, the application program polls t0con.0. when a "1" is detected, a timer 0 match or capture interrupt is pending. when the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, t0con.0. timer 0 control register (t0con) d2h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer 0 counter clear bit: 0 = no effect 1 = clear the timer 0 counter (when write) timer 0 input clock selection bits: 00 = fxx/1024 01 = fxx/256 10 = fxx/64 11 = external clock (p0.2/t0ck) timer 0 operating mode selection bits: 00 = interval mode (p0.3/t0) 01 = capture mode (capture on rising edge, counter running, ovf can occur) 10 = capture mode (capture on falling edge, counter running, ovf can occur) 11 = pwm mode (ovf interrupt can occur) timer 0 overflow interrupt enable bit: 0 = disable overflow interrupt 1 = enable overflow interrupt timer 0 match/capture interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer 0 match/capture interrupt pending bit: 0 = no interrupt pending 0 = clear pending bit (write) 1 = interrupt is pending figure 10-3. timer 0 control register (t0con)
s3c852b/P852B (p reliminary s pec ) basic timer and timer 0 10- 7 timer 0 function description timer 0 interrupts (irq0, vectors fah and fch) the timer 0 module can generate two interrupts: the timer 0 overflow interrupt (t0ovf), and the timer 0 match/ capture interrupt (t0int). t0ovf is interrupt level irq0, vector fah. t0int also belongs to interrupt level irq0, but is assigned the separate vector address, fch. a timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. however, the timer 0 match/capture interrupt pending condition must be cleared by the application?s interrupt service routine by writing a "0" to the t0con.0 interrupt pending bit. interval timer mode in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 reference data register, t0data. the match signal generates a timer 0 match interrupt (t0int, vector fch) and clears the counter. if, for example, you write the value "10h" to t0data, the counter will increment until it reaches ?10h?. at this point, the timer 0 interrupt request is generated, the counter value is reset, and counting resumes. with each match, the level of the signal at the timer 0 output pin is inverted (see figure 10-4). match signal m u x 8-bit up counter timer 0 buffer register 8-bit comparator timer 0 data register t0con.3 t0con.5-.4 t0con.0 capture signal t0con.1 t0int (irq0) t0 (p0.3) pending interrupt enable/disable match r (clear) clk (match int) figure 10-4. simplified timer 0 function diagram: interval timer mode
basic timer and timer 0 s3c852b/p8 52b (p reliminary s pec ) 10- 8 pulse width modulation mode pulse width modulation (pwm) mode lets you program the width (duration) of the pulse that is output at the t0 (p0.3) pin. as in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 data register. in pwm mode, however, the match signal does not clear the counter. instead, it runs continuously, overflowing at "ffh", and then continues incrementing from "00h". although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in pwm-type applications. instead, the pulse at the t0 (p0.3) pin is held to low level as long as the reference data value is less than or equal to ( ) the counter value and then the pulse is held to high level for as long as the data value is greater than ( > ) the counter value. one pulse width is equal to t clk 256 (see figure 10-5). match signal m u x 8-bit up counter timer 0 buffer register 8-bit comparator timer 0 data register t0con.3 t0con.5-.4 t0con.0 capture signal t0con.1 t0int (irq0) t0/pwm output (p0.3) pending interrupt enable/disable match t0ovf (irq0) clk t0ovf high level when data > counter, lower level when data < counter note: interrupts are usually not used when timer 0 is configured to operate in pwm mode. (match int) figure 10-5. simplified timer 0 function diagram: pwm mode
s3c852b/P852B (p reliminary s pec ) basic timer and timer 0 10- 9 capture mode in capture mode, a signal edge that is detected at the t0cap (p0.3) pin opens a gate and loads the current counter value into the timer 0 data register. you can select rising or falling edges to trigger this operation. timer 0 also gives you capture input source: the signal edge at the t0cap (p0.3) pin. you select the capture input by setting the values of the timer 0 capture input selection bits in the port 0 control register, p0conl.7?.6, (set 1, bank 0, ebh). when p0conl.7?.6 is "00" or "01", the t0cap input is selected. both kinds of timer 0 interrupts can be used in capture mode: the timer 0 overflow interrupt is generated whenever a counter overflow occurs; the timer 0 match/capture interrupt is generated whenever the counter value is loaded into the timer 0 data register. by reading the captured data value in t0data, and assuming a specific value for the timer 0 clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the t0cap pin (see figure 10-6). m u x t0con.5-.4 t0con.0 t0con.1 t0int (irq0) pending interrupt enable/disable match signal 8-bit up counter timer 0 data register clk t0ovf (irq0) t0con.5-.4 t0cap input (p0.3) (capture int) figure 10-6. simplified timer 0 function diagram: capture mode
basic timer and timer 0 s3c852b/p8 52b (p reliminary s pec ) 10- 10 t0/pwm output (p0.3) mux 1/1024 f xx 1/64 1/256 div t0ck input (p0.2) t0con.7-.6 m u x t0con.5-.4 t0con.0 t0con.1 t0int (irq0) pending t0con.5-.4 t0cap input (p0.3) timer 0 buffer register 8-bit comparator timer 0 data register 8-bit up counter (read-only) r counter clear signal 8 data bus 8 t0con.3 intpnd.0 t0con.2 t0int (irq0) pending ovf data bus (ovf int) (match/capture int) figure 10-7. timer 0 block diagram
s3c852b/P852B (p reliminary s pec ) basic timer and timer 0 10- 11 f f programming tip ? configuring the basic timer this example shows how to configure the basic timer to sample specifications: org 0100h reset di ; disable all interrupts ld btcon,#0aah ; disable the watchdog timer ld clkcon,#18h ; non-divided clock clr sym ; disable global and fast interrupts clr spl ; stack pointer low byte ? "0" ; stack area starts at 0ffh ? ? ? srp #0c0h ; set register pointer ? 0c0h ei ; enable interrupts ? ? ? main ld btcon,#52h ; enable the watchdog timer ; basic timer clock: f xx /4096 ; clear basic timer counter nop nop ? ? ? jp t,main ? ? ?
basic timer and timer 0 s3c852b/p8 52b (p reliminary s pec ) 10- 12 f f programming tip ? programming timer 0 this sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and determines the execution sequence which follows a timer 0 interrupt. the program parameters are as follows: ? timer 0 is used in interval mode; the timer interval is set to 4 milliseconds ? oscillation frequency is 4 mhz ? general register 64h (page 0) ? 60h + 62h + 63h + 64h (page 0) + 1h (value) is executed after a timer 0 interrupt org 0fah ; timer 0 overflow in terrupt vector t0over org 0fch ; timer 0 match/capture interrupt vector t0int org 0100h reset di ; disable all interrupts ld btcon,#0aah ; disable the watchdog timer ld clkcon,#18h ; select non-divided clock clr sym ; disable global and fast interrupts clr spl ; stack pointer low byte ? "0" ; stack area starts at 0ffh ? ? ? ld t0con,#4ah ; write ?01001010b? ; input clock is f xx /256 ; interval timer mode ; enable the timer 0 interrupt ; disable the timer 0 overflow interrupt l d t0data,#3fh ; set timer interval to 4 milliseconds ; (4 mhz/256) (62.5 + 1) = 0.25 khz (4 ms) srp #0c0h ; set register pointer ? 0c0h ei ; enable interrupts ? ? ? t0int push rp0 ; save rp0 to stack srp0 #60h ; rp0 ? 60h inc r0 ; r0 ? r0 + 1 add r2,r0 ; r2 ? r2 + r0 adc r3,r2 ; r3 ? r3 + r2 + carry adc r4,r3 ; r4 ? r4 + r3 + carry (continued on next page)
s3c852b/P852B (p reliminary s pec ) basic timer and timer 0 10- 13 f f programming tip ? programming timer 0 (continued) cp r0,#32h ; 50 4 = 200 ms jr ult,no_200ms_set bits r1.2 ; bit setting (61.2h) no_200ms_set: ld t0con,#4ah ; clear pending bit pop rp0 ; restore register pointer 0 value t0over iret ; return from interrupt service routine
basic timer and timer 0 s3c852b/p8 52b (p reliminary s pec ) 10- 14 notes
s3c852b/P852B (p reliminary s pec ) timer 1 11- 1 11 timer 1 one 16-bit timer mode (timer 1) the 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. if tacon.7 is set to "1", as a 16-bit timer. if tacon.7 is set to "0", timer 1 is used as two 8-bit timers. ? one 16-bit timer mode (timer 1 ) ? two 8-bit timers mode (timer a and b) overview the 16-bit timer 1 is an 16-bit general-purpose timer. timer 1 has the interval timer mode by using the appropriate tacon setting. timer 1 has the following functional components: ? clock frequency divider (fxx divided by 1024, 512, 8, or 1 and t1ck: external clock) with multiplexer ? 16-bit counter (tacnt, tbcnt), 16-bit comparator, and 16-bit reference data register (tadata, tbdata) ? timer 1 match interrupt (irq1, vector f4h) generation ? timer 1 contro l register, tacon (set 1, bank 1, e4h, read/write) function description interval timer function the timer 1 module can generate an interrupt: the timer 1 match interrupt (t1int). t1int belongs to interrupt level irq1, and is assigned the separate vector address, f4h. the t1int pending condition should be cleared by software when it has been serviced. even though t1int is disabled, the application's service routine can detect a pending condition of t1int by the software and execute it's sub-routine. when this case is used, the t1int pending bit must be cleared by the application sub-routine by writing a "0" to the tacon.0 pending bit. in interval timer mode, a match signal is generated when the counter value is identical to the values written to the timer 1 reference data registers, tadata and tbdata(ffh). the match signal generates a timer 1 match interrupt (t1int, vector f4h) and clears the counter. if, for example, you write the value 32h to tadata, and 8eh to tacon, the counter will increment until it reaches 32ffh. at this point, the timer 1 interrupt request is generated, the counter value is reset, and counting resumes.
timer 1 s3c852b/p852 b (p reliminary s pec ) 11- 2 timer 1 control register (tacon) you use the timer 1 control register, tacon, to ? enable the timer 1 operating (interval timer) ? select the timer 1 input clock frequency ? clear the timer 1 counter, tacnt and tbcnt ? enable the timer 1 interrupt ? clear timer 1 interrupt pending conditions tacon is located in set 1, bank 1, at address e4h, and is read/write addressable using register addressing mode. a reset clears tacon to "00h". this sets timer 1 to disable interval timer mode, selects an input clock frequency of fxx/1024, and disables timer 1 interrupt. you can clear the timer 1 counter at any time during normal operation by writing a "1" to tacon.3. to enable the timer 1 interrupt (irq1, vector f4h), you must write tacon.7, tacon.2, and tacon.1 to "1". to generate the exact time interval, you should write tacon.3 and tacon.0, which cleared counter and interrupt pending bit. to detect an interrupt pending condition when t1int is disabled, the application program polls pending bit, tacon.0. when a "1" is detected, a timer 1 interrupt is pending. when the t1int sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 1 interrupt pending bit, tacon.0. timer a control register (tacon) e4h, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer a interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer a interrupt pending bit: 0 = no interrupt pending 0 = clear pending bit (when write) 1 = interrupt is pending timer a counter enable bit: 0 = disable counting operation 1 = enable counting operation timer a counter clear bit: 0 = no affect 1 = clear the timer a counter (when write) one 16-bit timer or two 8-bit timers mode: 0 = two 8-bit timers mode (timer a/b) 1 = one 16-bit timer mode (timer 1) timer a clock selection bits: 000 = fxx/1024 001 = fxx/512 010 = fxx/8 011 = fxx 1xx = t1ck (external clock) ('x' means don't care.) figure 11-1. timer 1 control register (tacon)
s3c852b/P852B (p reliminary s pec ) timer 1 11- 3 block diagram note: when tacon.7 is '1', one 16-bit timer a. tacon.6-.4 m u x tacon.3 t1ck p0.4 comparator f xx /1 f xx /8 f xx /512 f xx /1024 tbcnt(ffh) tacnt tbdata(ffh) tadata lsb msb tacon.1 ta (interval) p0.5 match irq1 (match int) lsb msb clear figure 11-2. timer 1 functional block diagram
timer 1 s3c852b/p852 b (p reliminary s pec ) 11- 4 two 8-bit timers mode (timer a and b) overview the 8-bit timer a and b are the 8-bit general-purpose timers. timer a have the interval timer mode, and the timer b have the interval timer mode and pwm mode by using the appropriate tacon and tbcon setting, respectively. timer a and b have the following functional components: ? clock frequency divider with multiplexer ? fxx divided by 1024, 512, 8, or 1 and t1ck (external clock) for timer a ? fxx divided by 8, 4, 2, or 1 for timer b ? 8-bit counter (tacnt, tbcnt), 8-bit comparator , and 8-bit reference data register (tadata, tbdata) ? timer a have i/o pin for match output (p0.5, ta) ? timer a match interrupt (irq1, vector f4h) generation ? timer a control register, tacon (set 1, bank 1, e4h, read/write) ? timer b have i/o pin for match and pwm output (p0.6, tb) ? timer b overflow interrupt (irq1, vector f6h) generation ? timer b match interrupt (irq1, vector f8h) generation ? timer b control register, tbcon (set 1, bank 1, e5h, read/write) timer a and b control register (tacon, tbcon) you use the timer a and b control register, tacon and tbcon, to ? enable the timer a (interval timer mode) and b operating (interval timer mode and pwm mode) ? select the timer a and b input clock frequency ? clear the timer a and b counter, tacnt and tbcnt ? enable the timer a and b interrupt ? clear timer a and b interrupt pending conditions
s3c852b/P852B (p reliminary s pec ) timer 1 11- 5 tacon and tbcon are located in set 1, bank 1, at address e4h and e5h, and is read/write addressable using register addressing mode. a reset clears tacon to "00h". this sets timer a to disable interval timer mode, selects an input clock frequency of fxx/1024, and disables timer a interrupt. you can clear the timer a counter at any time during normal operation by writing a "1" to tacon.3. a reset clears tbcon to "00h". this sets timer b to disable interval timer mode and pwm mode, selects an input clock frequency of fxx/8, and disables timer a interrupt. you can clear the timer b counter at any time during normal operation by writing a "1" to tbcon.3. to enable the timer a interrupt (taint) and timer b interrupt (tbint), (irq1, vector f4h, f8h), you must write tacon.7 to "0", tacon.2 (tbcon.2) and tacon.1 (tbcon.1) to "1". to generate the exact time interval, you should write tacon.3 (tbcon.3) and tacon.0 (intpnd.2), which cleared counter and interrupt pending bit. to detect an interrupt pending condition when taint and tbint is disabled, the application program polls pending bit, tacon.0 and intpnd.2. when a "1" is detected, a timer a interrupt (taint) and timer b interrupt (tbint) is pending. when the taint and tbint sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer a and b interrupt pending bit, tacon.0 and intpnd.2. also, to enable timer b overflow interrupt (tbovf), (irq1, vector f6h), you must write tacon.7 to "0", tbcon.2 and tbcon.0 to "1". to generate the exact time interval, you should write tbcon.3 and intpnd.2, witch cleared counter and interrupt pending bit. timer a control register (tacon) e4h, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer a interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer a interrupt pending bit: 0 = no interrupt pending 0 = clear pending bit (when write) 1 = interrupt is pending timer a counter enable bit: 0 = disable counting operation 1 = enable counting operation timer a counter clear bit: 0 = no affect 1 = clear the timer a counter (when write) one 16-bit timer or two 8-bit timers mode: 0 = two 8-bit timers mode (timer a/b) 1 = one 16-bit timer mode (timer 1) timer a clock selection bits: 000 = fxx/1024 001 = fxx/512 010 = fxx/8 011 = fxx 1xx = t1ck (external clock) ('x' means don't care.) figure 11-3. timer a control register (tacon)
timer 1 s3c852b/p852 b (p reliminary s pec ) 11- 6 timer b control register (tbcon) e5h, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb timer b match interrupt enable bit: 0 = disable match interrupt 1 = enable match interrupt timer b overflow interrupt enable bit: 0 = disable overflow interrupt 1 = enable overflow interrupt timer b count enable bit: 0 = disable counting operating 1 = enable counting operating timer b counter clear bit: 0 = no effect 1 = clear the timer b counter (when write) timer b clock selection bits: 00 = f x x/8 01 = f x x/4 10 = f x x/2 11 = fxx timer b operating mode selection bits: 00 = interval mode 01 = 6-bit pwm mode (ovf interrupt can occur) 10 = 7-bit pwm mode (ovf interrupt can occur) 11 = 8-bit pwm mode (ovf interrupt can occur) figure 11-4. timer b control register (tbcon)
s3c852b/P852B (p reliminary s pec ) timer 1 11- 7 function description interval timer function (timer a and timer b) the timer a and b module can generate an interrupt: the timer a match interrupt (taint) and the timer b match interrupt (tbint). taint belongs to interrupt level irq1, and is assigned the separate vector address, f4h. tbint belongs to interrupt level irq1 and is assigned the separate vector address, f8h. the timer a match interrupt pending condition (tacon.0) and the timer b match interrupt pending condition (intpnd.2) must be cleared by software in the application's interrupt service by means of writing a "0" to the tacon.0 and intpnd.2 interrupt pending bit. even though taint and tbint are disabled, the application's service routine can detect a pending condition of taint and tbint by the software and execute it's sub-routine. when this case is used, the taint and tbint pending bit must be cleared by the application sub-routine by writing a "0" to the corresponding pending bit tacon.0 and intpnd.2. in interval timer mode, a match signal is generated when the counter value is identical to the values written to the timer a or timer b reference data registers, tadata or tbdata. the match signal generates corresponding match interrupt (taint, vector f4h; tbint, vector f8h) and clears the counter. if, for example, you write the value 20h to tadata and 0eh to tacon, the counter will increment until it reaches 20h. at this point, the timer a interrupt request is generated, the counter value is cleared, and counting resumes and you write the value 10h to tbdata, "0" to tacon.7, and 0eh to tbcon, the counter will increment until it reaches 10h. at this point, tb interrupt request is generated, the counter value is cleared and counting resumes.
timer 1 s3c852b/p852 b (p reliminary s pec ) 11- 8 note: when tacon.7 is '0', two 8-bit timer a/b (interval mode). tacon.6-.4 m u x tacon.3 t1ck p0.4 comparator f xx /1 f xx /8 f xx /512 f xx /1024 tacnt tadata tacon.1 ta (interval) p0.5 match r clear comparator f xx /1 f xx /2 f xx /4 f xx /8 tb (interval) p0.6 match tbcon.1 tbcon.3 clear tbcnt tbdata r tbcon.5-.4 m u x irq1 tbcon.6,.7 m u x (match int) figure 11-5. timer a and b function block diagram
s3c852b/P852B (p reliminary s pec ) timer 1 11- 9 pulse width modulation mode (timer b) pulse width modulation (pwm) mode lets you program the width (duration) of the pulse that is output at the tb (p0.6) pin. as in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer b data register. in pwm mode, however, the match signal does not clear the counter. instead, it runs continuously, overflowing at "ffh", and then continues incrementing from "00h". although you can use the match signal to generate a timer b overflow interrupt, interrupts are not typically used in pwm-type applications. instead, the pulse at the tb pin is held to low level as long as the reference data value is less than or equal to ( ) the counter value and then the pulse is held to high level for as long as the data value is greater than (>) the counter value. one pulse width is equal to t clk 256 (see figure 11-6). tbcon.5-.4 tbcon.3 8-bit comparator up-counter (read-only) mux match r clear selected tbovf tbcon.6-.7 irq1 (ovf int) f xx /1 f xx /2 f xx /4 f xx /8 m u x timer b buffer register timer b data register (read/write) data bus 6-bit match 7-bit match 8-bit match 6-bit ovf 7-bit ovf 8-bit ovf mux mux tbcon.6-.7 intpnd.1 tbcon.0 tbcon.3 tbcon.6-.7 p0.6 intpnd.2 tbcon.1 irq1 (match int) pending bit tb(pwm, interval) figure 11-6. timer b pwm function block diagram
timer 1 s3c852b/p852 b (p reliminary s pec ) 11- 10 notes
s3c852b/P852B (p reliminary s pec ) watch timer 12- 1 12 watch timer overview watch timer functions include real-time and watch-time measurement and interval timing for the system clock. to start watch timer operation, set bit 1 of the watch timer control register, wtcon.1 to "1". and if you want to service watch timer overflow interrupt (irq3, vector f2h), then set the wtcon.6 to ?1?. the watch timer overflow interrupt pending condition (wtcon.0) must be cleared by software in the application?s interrupt service routine by means of writing a "0" to the wtcon.0 interrupt pending bit. after the watch timer starts and elapses a time, the watch timer interrupt pending bit (wtcon.0) is automatically set to "1", and interrupt requests commence in 3.91ms, 0.25, 0.5 and 1-second intervals by setting watch timer speed selection bits (wtcon.3 ? .2). the watch timer can generate a steady 2 khz, 4 khz, 8 khz, or 16 khz signal to buz output pin for buzzer. by setting wtcon.3 and wtcon.2 to "11b", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. high-speed mode is useful for timing events for program debugging sequences. also, you can select watch timer clock source by setting the wtcon.7 appropriatly value. watch timer has the following functional components: ? real time and watch-time measurement ? using a main system or subsystem clock source (main clock divided by 2 7 (fx/128) or sub clock(fxt)) ? i/o pin for buzzer output frequency generator (p0.1, buz) ? timing tests in high-speed mode ? watch timer overflow interrupt (irq1, vector f2h) generation ? watch timer control register, wtcon (set 1, bank 1, e6h, read/write)
watch timer s3c852 b/P852B (p reliminary s pec ) 12- 2 watch timer control register (wtcon) the watch timer control register, wtcon is used to select the input clock source, the watch timer interrupt time and buzzer signal, to enable or disable the watch timer function. it is located in set 1, bank 1 at address e6h, and is read/write addressable using register addressing mode. a reset clears wtcon to "00h". this disable the watch timer and select fx/128 as the watch timer clock. so, if you want to use the watch timer, you must write appropriate value to wtcon. to values of watch timer speed are accurate when watch timer clock is fxt. so, if you select fx/128 as watch timer clock, the speed will be changed according to the frequency fx. buzzer signal selection bits: 00 = 2 khz 01 = 4 khz 10 = 8 khz 11 = 16 khz watch timer control register (wtcon) e6h, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb watch timer enable/disable bit: 0 = disable watch timer; clear frequency dividing circuits 1 = enable watch timer watch timer interrupt pending bit: 0 = interrupt request is not pending 1 = interrupt request is pending watch timer speed selection bits: 00 = set watch timer interrupt to 1 s 01 = set watch timer interrupt to 0.5 s 10 = set watch timer interrupt to 0.25 s 11 = set watch timer interrupt to 3.91 ms watch timer clock selection bit: 0 = main clock divided by 2 7 (fx/128) 1 = sub clock (fxt) watch timer int enable/disable bit: 0 = disable watch timer int 1 = enable watch timer int figure 12-1. watch timer control register (wtcon)
s3c852b/P852B (p reliminary s pec ) watch time r 12- 3 watch timer circuit diagram wt int enable wtcon.1 wtcon.2 wtcon.3 wtcon.4 wtcon.5 wtcon.6 enable/disable selector circuit mux wtcon.0 irq3 wtcon.6 buzzer output f w /2 15 f w /2 14 f w /2 13 f w /2 7 f w /16 (2 khz) f w /8 (4 khz) f w /4 (8 khz) f w /2 (16 khz) (1 hz) f x = main system clock fxt = subsystem clock (32,768 hz) f w = watch timer frequency clock selector frequency dividing circuit f w 32.768 khz f xt f x / 128 (1) fw wtcon.7 wtcon.0 (pending bit) pending bit n ote: the buzzer output enable/disable is controled by setting p0conl.3-.2. that is, if the value of p0conl.3-.2 is "11" (p0.1 is configured to select alternative function), the buzzer output enabled, at this time, watch timer must be enabled. the other value except "11" of p0conl.3-.2 disable the buzzer output. 8 buz (p0.1) figure 12-2. watch timer circuit diagram
watch timer s3c852 b/P852B (p reliminary s pec ) 12- 4 notes
s3c852b/P852B ( preliminary spec) serial i/o port 13- 1 13 serial i/o port overview serial i/o module, sio can interface with various types of external devices that require serial data transfer. sio has the following functional components: ? sio data receiv e/transmit interrupt (irq4, vector f0h) generation ? 8 -bit control register, siocon (set 1, bank 1, ebh, read/write) ? clock selection logic ? 8-bit data buffer, siodata ? 8-bit prescaler (siops), (set 1, bank 1, ech, read/write) ? 3-bit serial clock counter ? serial data i/o pins (p1.4?p1.5, si, so) ? external clock input/output pin (p1.6, sck ) the sio module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. to ensure flexible data transmission rates, you can select an internal or external clock source. programming procedure to program the sio modules, follow these basic steps: 1. configure p1.4, p1.5 and p1.6 to alternative function (si, so, sck ) for interfacing sio module by setting the p1afs register to appropriatly value. 2. load an 8-bit value to the siocon control register to properly configure the serial i/o module. in this operation, siocon.2 must be set to "1" to enable the data shifter. 3. for inter rupt generation, set the serial i/o interrupt enable bit, siocon.1 to "1". 4. to transmit data to the serial buffer, write data to siodata and set siocon.3 to 1, then the shift operation starts. 5. when the shift operation (transmit/receive) is completed, the sio pending bit (siocon.0) is set to "1" and an sio interrupt request is generated.
serial i/o port s3c 852b/P852B ( preliminary spec) 13- 2 sio control register (siocon) the control register for the serial i/o interface module, siocon, is located in set 1, bank 1 at address ebh. it has the control settings for sio module. ? clock source selection (internal or external) for shift clock ? interrupt enable ? edge selection for shift operation ? clear 3-bit counter and start shift operation ? shift operation (transmit) enable ? mode selection (transmit/receive or receive-only) ? data direction selection (msb first or lsb first) a reset clears the siocon value to '00h'. this configures the corresponding module with an internal clock source, p.s clock, at the sck , selects receive-only operating mode, the data shift operation and the interrupt are disabled, and the data direction is selected to msb-first. so, if you want to use sio module, you must write appropriate value to siocon. serial i/o module control registers (siocon) ebh, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb sio interrupt enable bit: 0 = disable sio interrupt 1 = enable sio interrupt sio interrupt pending bit: 0 = no interrupt pending 0 = clear pending condition (when write) 1 = interrupt is pending sio shift operation enable bit: 0 = disable shifter and clock counter 1 = enable shifter and clock counter shift clock edge selection bit: 0 = t x at falling edeges, r x at rising edges 1 = t x at rising edeges, r x at falling edges data direction control bit: 0 = msb-first mode 1 = lsb-first mode sio mode selection bit: 0 = receive-only mode 1 = transmit/receive mode sio counter clear and shift start bit: 0 = no action 1 = clear 3-bit counter and start shifting sio shift clock selection bit: 0 = internal clock (p.s clock) 1 = external clock ( sck ) figure 13-1. serial i/o module control registers (siocon)
s3c852b/P852B ( preliminary spec) serial i/o port 13- 3 sio prescaler register (siops) the control register for the serial i/o interface module, siops, is located in set 1, bank 1, at address ech. the value stored in the sio prescaler registers, siops, lets you determine the sio clock rate (baud rate) as follows: baud rate = input clock (fxx)/[(siops value + 1) 4] or sck input clock. sio pre-scaler register (siops) ech, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb siops data value baud rate = input clock (fxx)/[(siops + 1) x 4] or sclk input clock figure 13-2. sio prescaler register (siops) block diagram sio int pending 3-bit counter clear siocon.0 8-bit sio shift buffer (siodata) fxx /2 siops sck (p1.6) siocon.7 (shift clock source select) prescaled value = 1/(siops +1) clk siocon.1 (interrupt enable) clk si (p1.4) siocon.3 siocon.4 (shift clock edge select) siocon.5 (mode select) siocon.2 (shift enable) siocon.6 (lsb/msb first mode select) data bus 8 so (p1.5) m u x 1/2 8-bit p.s. irq4 figure 13-3. sio functional block diagram
serial i/o port s3c 852b/P852B ( preliminary spec) 13- 4 serial i/o timing diagrams so (data output) si (data input) shift clock transmit complete irq4 set siocon.3 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 figure 13-4. sio timing in transmit/receive mode (tx at falling edge, siocon.4=0) so (data output) si (data input) shift clock transmit complete irq4 set siocon.3 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 figure 13-5. sio timing in transmit/receive mode (tx at rising edge, siocon.4=1)
s3c852b/P852B ( preliminary spec) serial i/o port 13- 5 so si shift clock transmit complete irq4 set siocon.3 d7 d6 d5 d4 d3 d2 d1 d0 high impedance figure 13-6. sio timing in receive-only mode (rising edge start) f f programming tip ? use internal clock to transfer and receive serial data 1. the method that uses hardware pending check is used. di ; disable all interrupts ld p1afs, #70h ; p1.4?p1.6 are selected to alternative function for ; si, so, sck , respectively ei sb1 ld siodata,tdata ; load data to sio buffer ld siops,#90h ; baud rate = input clock(fxx)/[(144 + 1) x 4] ld siocon,#2eh ; interval clock, msb first, transmit/receive mode sb0 ; select falling edges to start shift operation ; clear 3-bit counter and start shifting ; enable shifter and clock counter ; enable sio interrupt and clear pending sioint push rp0 ; srp0 #rdata ; s b1 ld r0,siodata ; load received data to general register or siocon,#08h ; sio restart pop rp0 iret
serial i/o port s3c 852b/P852B ( preliminary spec) 13- 6 f f programming tip ? use internal clock to transfer and receive serial data (continued) 2. the method that uses software pending check is used. di ; disable all interrupts ld p1afs, #70h ; p1.4?p1.6 are selected to alternative function for ; si, so, sck , respectively ei sb1 ld siodata,tdata ; load data to sio buffer ld siops,#90h ; baud rate = input clock(fxx)/[(144 + 1) 4] ld siocon,#2ch ; internal clock, msb first, transmit/receive mode ; select falling edges to start shift operation ; clear 3-bit counter and start shifting ; disable sio interrup siotest: ld r6,siocon ; to check whether transmit and receive is finished btjrf siotest,r6.0 ; check pending bit nop and siocon, #0feh ; pending clear by software ld rdata,siodata ; load received data to rdata sb0
s3c852b/P852B (p reliminary s pec ) caller id block 14- 1 14 caller id block overview the s3c852b/P852B microcontroller has a caller id on call waiting (cidcw) receiver, tone generator, etc. the s3c852b is used for receiving physical layer signals like bellcore's cpe alerting signal (cas) and similar evolving systems and also meets the requirements of emerging caller id on call waiting (cidcw) services. in addition, two different signal inputs are available to support tip/ring and hybrid connectivity. the device also includes a 1200 baud bell 202/v.23 compatible fsk data demodulator, a ring or line reversal detector, a line voltage measurement unit, a tia/eia pn-4159 compatible stutter dial tone detector, and a tone generator is capable of generating fsk signal and dual tone signals such as cas, dtmf to support various applications such as short messaging service (sms).
caller id blcok s3c852b/P852B (p reliminary s pec ) 14- 2 adc tone geneator gain controller pdm bandpass filter fsk receiver bandpass filter lrin out inn inp ins cas detector sdt detector line reversal / ring detector bias voltage vdda vssa melody generator mode control figure 14-1. cid part functional block diagram
s3c852b/P852B (p reliminary s pec ) caller id block 14- 3 function description of cid block analog input and preprocessor the preprocessor for the fsk receiver ,the cas and the sdt detectors, comprises two input signal buffers, an 14-bit analog-to-digital converter (14-bit adc) and digital bandpass filters. bandpass filters are used to attenuate out band noise and interfering signals, which might otherwise reach the fsk receiver and cas, sdt detectors. the cas and sdt detectors share a single digital filter while the fsk receiver has its own separate filter. in cid block?s power down mode, the cid block can be forced into a power-down state by switching off the 3.579545 mhz main clock and adc?s and op-amps. differential i nput b uffer the differential input buffer is used to convert the balanced telephone line signal to the input signal of 14-bit adc in the s3c852b. s3c852b tip/a ring/b r1a c1a to 14-bit adc r3 r1b inp c1b r4 r5 inn out vref + - figure 14-2. differential i nput b uffer of the s3c852b design equations for this buffer are; the differential voltage gain = r5/r1b. r1a = r1b c1a = c1b r3 = r4 * r5/(r4 + r5) the target differential voltage gain should be adjusted to obtain the expected signal level at the "out" pin.
caller id blcok s3c852b/P852B (p reliminary s pec ) 14- 4 single e nded i nput b uffer the single ended input buffer may also be used with the telephone line signal connected to the hybrid as shown in figure 14-3. s3c852b a connected to hybrid r6 c4 to 14-bit adc r7 ins vref + - figure 14-3. single e nded b uffer of the s3c852b the voltage gain is r7/( r6 + r7 ) the target voltage gain should be adjusted to obtain the expected signal level at the ins input. the bfs (buffer selection) bit in the function register chooses between the output of the single-ended input buffer and the output of the differential input buffer, sending the selected output to the 14-bit adc. the differential input buffer is selected when bfs is "0" and the single ended input buffer is selected when bfs is "1". the default value of bfs is "0"
s3c852b/P852B (p reliminary s pec ) caller id block 14- 5 cas tone detection the s3c852b cas detection algorithm is capable of detecting the cas signals during speech with high talk- down and talk-off performance, and 100% bellcore compliant performance with use of a hybrid. if the cas detection is enabled the cid block will generate an interrupt (interrupt register, bit 1 is set) when a correct dual tone (2130 and 2750 hz) is detected. cas detection is enabled when the casenable bit in the function register is set and the fsk and sdt enable bits in the function register are cleared. the parameters of the cas detector are shown in table 14-1. table 14-1. cas detector parameters parameter value low tone frequency 2130hz 0.5% high tone frequency 2750hz 0.5% accepted signal level -5.2dbm to ?38dbm twist -6db to +6db when a valid cas signal is detected, the casdetect status bit of the status register and the casint bit of the interrupt register are set and an interrupt is generated. when the signal level is below the accepted signal level the status bit of the status register is cleared and the casint interrupt bit is set , generating another interrupt. the casint interrupt bit is reset when the interrupt register is read (see figure 14-4). in order to accurately detect the end of a cas tone, it is recommended to mute the near end speech immediately after the cas tone has been detected. to disable the cas detection function, set the casenable bit to 0 when the casdetect bit is 0, or after the second cas interrupt. cas signal line signal casdetect int figure 14-4. casdetect, casint and int r elated to the cas tone
caller id blcok s3c852b/P852B (p reliminary s pec ) 14- 6 fsk data reception fsk d ata r eception s equence the on-chip fsk receiver satisfies all target specifications of bellcore. the fsk receiver function can be enabled by setting the fskenable bit (function register, bit2) and clearing the casenable (function register, bit1) and the sdtenable (function register, bit5) bits. when the fsk receiver is enabled, the cid block continuously checks for a signal in the fsk band (~1200 - ~2200 hz) above the minimum signal level threshold. an fsk data word consists of one start bit (space) followed by eight data bits and one stop bit (mark). after the fsk receiver has detected a start bit it starts receiving the data bits (lsb first). after the 8 th data bit the fskint interrupt bit (interrupt register, bit2) is set and an interrupt is generated. the fskint interrupt bit is cleared when the interrupt register is read. the interrupt register and the fskdt register should be read every time an interrupt occurs. d0 fsk data fskint int d1 d2 d3 d4 d5 d6 d7 interrupt register is read. figure 14-5. sequence to r eceive an fsk d ata b yte the parameters of the fsk receiver are shown in table 14-2. table 14-2. fsk receiver p arameters parameter bellcore ccitt/ v23 mark frequency (logic 1) 1200hz 1% 1300hz 1.5% space frequency (logic 0) 2200hz 1% 2100hz 1.5% maximum allowed signal level 0dbm -8dbv minimum signal level threshold <-45dbm <-52dbv twist -10db to +10db -6db to +6db accepted s/n (0hz ? 200hz) <-20db <-20db accepted s/n (200hz ? 3200hz) <6db <6db accepted s/n (3200hz ? 15000hz) <-20db <-20db transmission rate 1200 bits per second 1% 1200 bits per second 1%
s3c852b/P852B (p reliminary s pec ) caller id block 14- 7 begin of mark (bom) d etection bomdc bit of mode register (mode register, bit 6) is utilized for detecting begin of mark or channel seizure. if bomdc is cleared, the bomdetect signal (stat register, bit 4) will be set after the begin of mark has been detected, and if bomdc is '1', bomdetect will be set after the channel seizure detected. when bomdc is '1' and bomdetect is set, the interrupts occur due to channel seizure as shown in figure 14-6. if bomdc is '0', interrupt will therefore not be generated during the channel seizure and during the block of marks as shown in figure 9. the fsk interrupts of data bytes will be generated after a mark period of at least 16 sequential 1?s has been detected. behavior of bomdetect (stat register, bit 4) is shown in figure 14-7. this bit will be cleared when the fsk receiver is disabled or a signal drop out occurs for more than 18.3ms. in the latter case the fsk receiver will behave as if it has just been disabled. fsk transmission line signal mark lnterrupts due to channel seizure channel seizure(optional) data noise noise fsk enabie bom detect ... ... int when bomdc = 1 figure 14-6. interrupt behavior of the fsk receiver with bomdc = 1 fsk transmission line signal mark channel seizure(optional) data noise noise fsk enabie bom detect ... int when bomdc = 0 figure 14-7. interrupt behavior of the fsk receiver with bomdc = 0
caller id blcok s3c852b/P852B (p reliminary s pec ) 14- 8 stutter dial tone(sdt) detector this block is enabled when the s3c852b is set to sdt enable mode (function register, bit5) and all the other functions in the function register are disabled. the detector measures the total signal level for every 31.5ms. when the total signal level is above -36dbm and the frequencies of dual tone are 350hz and 440hz dial tone band, the sdtdetect bit in the status register is set. when the total signal level is below ?38dbm the sdtdetect bit is cleared (see table 14-3). each time sdtdetect changes the sdtint bit is set and an interrupt is generated. the sdtint bit is cleared when the interrupt register is read. this behavior is shown in figure 14-8. line signal sdt signal ptedetect int lnterrupt register is read. sdt signal lnterrupt register is read. lnterrupt register is read. lnterrupt register is read. figure 14-8. sdt d etector o peration table 14-3. stutter dial t one p arameters parameters values frequencies 350hz + 440hz dual tone signal amplitude power -1dbm to -48dbm duration 80 to 160ms on/off, with a duty cycle from 40% to 60%
s3c852b/P852B (p reliminary s pec ) caller id block 14- 9 ring or line reversal detector for ring or line reversal detection, some external components are needed to generate a pulse each time a ring or line reversal occurs, as shown in figure 14-9. interrupt generation of the ring or line reversal detector is controlled by the lrenable bit in the function register. when lrenable is set to "1", the lrint bit of the interrupt register will be set and interrupts will be generated at every transition of the lrstatus bit. when lrenable is "0", interrupts will not generated. the lrstatus bit (reset value is high) in the status register is cleared to "0" at any positive edge of the lrin. if no positive edges of lrin are detected in tguard time the lrstatus bit is set to "1". the lrint bit is cleared when the interrupt register is read. s3c852b lrin tip/a ring/b r8 c2 to ring/line reversal detector r9 d6 d5 p1 r11 r10 c3 figure 14-9. external c omponent to g enerate lrin if an lrint interrupt has been generated in power-down mode, it is recommended to disable power-down mode to be able to count the guard time counter using the sub clock (xtin). the guard time counter is reset when l r in is high. the guard time ( tguard) can be programmed by writing the gtime register as follows. tguard = 183us * ( gtime[6:0] * 4 + 3 ) (ex. tguard = 44.469ms = 0.153ms * (0111100b * 4 + 3 ) ) figure 14-10 and figure 14-11 show line reversal and ring detection respectively. the l r in of figure 14-11 shows the behavior of lrin signal when the reference circuit of figure 14-9 is used.
caller id blcok s3c852b/P852B (p reliminary s pec ) 14- 10 line signal lrstatus int lnterrupt register is read. lrin lrint pwd = 0 pwd = 1 lrenable = 1 t guard figure 14-10. behavior of s ignals on a l ine r eversal line signal lrstatus int lnterrupt register is read. lrin lrint t guard lnterrupt register is read. figure 14-11. behavior of s ignals d uring r ing
s3c852b/P852B (p reliminary s pec ) caller id block 14- 11 tone generator s3c852b has a tone generator capable of generating general single tone such as fsk and general dual tone such as cas or dtmf. the block diagram of tone generator is shown in figure 14-12. the tone generator contains a numerically controlled oscillator (nco) to generate the addresses of two sine lookup tables (lut) for producing dual tone. the input tone of nco is selected by tones register value. the output power of each low and high tone can be controlled through two gain controllers (multipliers), and the added value of dual tone is converted to analog sine wave through pulse density modulator (pdm) and external rc circuit. to enable the tone generator, toneenable bit of function register (func register, bit 3) must be set to '1' for the first. if toneenable bit is '0', no tone will be generated. toneenable bit must be set before writing the control and data registers related to tone generation. to generate dual tone, dual tone on-off ( dtononoff) bit (tones register bit 1) must be set to '1' and fsk on-off ( fskonoff) bit (tones register bit 0) bit to '0'. for fsk generation, set fskonoff bit to '1' and clear dtononoff bit to '0'. fskmod s3c852b nco htone<15:0> ltone<15:0> input selection sine lut fsk sequence generator sine lut tones tonegl tonegh low tone high tone pdm toneo fsktint fsktd r11 c8 figure 14-12. tone g enerator b lock
caller id blcok s3c852b/P852B (p reliminary s pec ) 14- 12 numerically controlled oscillator s3c852b contains two sets of nco for generating dual tone, which receives 16-bit phase data ( dfreq) written by the mcu and continuously add and accumulate it using 24-bit phase accumulator at every clock cycle. the 5 most significant bits of accumulator is utilized as the address (n) of sine lut, which contains 32 amplitude values of sine(2 p n/32). the resolution (minimum frequency) and output frequency (f out ) of the nco is described below, when f clk is frequency of input clock (f clk = 1.789973 mhz = 3.579545/2 mhz). resolution = f clk /2 24 = 0.107hz f out = dfreq* f clk /2 24 so the phase input ( dfreq) is determined as follows dfreq = f out *2 24 /f clk the block diagram of nco is shown in figure 14-13. 16- bit (dfreq) 24-bit phase accumulator 5-bit msb's address of sine lut f clk = 1.789973mhz s3c852b figure 14-13. block d iagram of nco for example, 16-bit data of ltone1<7:0> and ltone0<15:0> for low frequency of dtmf character "1" (= 697hz) are determined as follows; f out = 697hz f clk = 1789973hz dfreq = f out *2 24 /f clk = 6534 = 1986h ltone1<7:0> = 19h ltone0<7:0> = 86h
s3c852b/P852B (p reliminary s pec ) caller id block 14- 13 dual t one g eneration f unction the tone generator can be utilized as cas, dtmf or other dual or other single sine wave generator. to enable the function of generating general dual tone, toneenable bit (func.3) must be set to '1', and the dual tone will be generated by setting dual tone on-off bit ( dtononoff) in tone select register (tones, bit 1) to '1' and fsk on-off ( fskonoff) bit (tones register, bit 0) of tones to '0'. if dtononoff bit is programmed to '0', dual tone generation function will be off. the 16-bit phase input data of high tone must be written in high tone data registers, which are htone1 (msb) and htone0 (lsb), the data of low tone in low tone data registers, which are ltone1 (msb) and ltone0 (lsb). the tone gain registers (tonegh for high tone and tonegl for low tone) can control the output gain of high and low tone. the default power of each tone is ?4.3dbm with +/-5% deviation when v dd is 3.3v on dtmf generation. the tonegh & tonel registers contain the gain factors those are multiplied to the default signal power to obtain the dual tone signal power. the gain factor is an unsigned number. the most significant bit (m) of the tonegh/l register is the mantissa and the remaining bits (e3 to e0) denote the exponent. the output power of the each tone signal can be obtained by the following equation. tone signal power = default signal power * tonegh/l symbol 7 6 5 4 3 2 1 0 tonegh (l) ? ? ? m e3 e2 e1 e0 the tonegh & tonel register can be programmed within the range from 0.0001b (0.0625 in decimal) to 1.0000b (1.0000 in decimal). don't write the gain value above 1.0000, because the default power is the maximum available power. for example, if tonegh & tonel is set to 10h (1.0000 in binary or 1.0 in decimal) signal power of dual tone will be the same as the default power. if the tonegh register is 0.0111h (0.4375 in decimal) and the tonegl register 0.0110h (0.3750 in decimal), the signal power will be determined as follows. 20log(default power*0.4375) ? 20log(default power) = 20log0.4375 = -7.16db 20log(default power*0.3750) ? 20log(default power) = 20log0.3750 = -8.50db the high tone power = -11.66db the low tone power = -13.00db the default (reset) values of tonegh & tonegl are 00h . the output power of toneo signal also can be varied by change of the external r or c values and additional hardwares.
caller id blcok s3c852b/P852B (p reliminary s pec ) 14- 14 dtmf t one g eneration to generate dtmf signal, toneenable bit (func.3) and dtoneonoff bit (tones.2) must be set to '1' and the phase input data ( dfreq) for high and low tone, which are corresponding to dtmf frequencies, must be written in htone1, htone0, ltone1 and ltone0 as shown in table 14-4. table 14-4. dtmf frequencies code and phase input data character low frequency ltone1:0 high frequency htone1:0 1 697hz 1986h 1209hz 2c46h 2 697hz 1986h 1336hz 30ech 3 697hz 1986h 1477hz 3615h 4 770hz 1c32h 1209hz 2c46h 5 770hz 1c32h 1336hz 30ech 6 770hz 1c32h 1477hz 3615h 7 852hz 1f32h 1209hz 2c46h 8 852hz 1f32h 1336hz 30ech 9 852hz 1f32h 1477hz 3615h 0 941hz 2274h 1336hz 30ech * 941hz 2274h 1209hz 2c46h # 941hz 2274h 1477hz 3615h a 697hz 1986h 1633hz 3bcch b 770hz 1c32h 1633hz 3bcch c 852hz 1f32h 1633hz 3bcch d 941hz 2274h 1633hz 3bcch cas tone generation to generate cas signal, toneenable bit (func.3) and dtoneonoff bit (tones.1) must be set to '1' and the phase input data ( dfreq) for the high and low tone, which are corresponding to cas frequencies, must be written in htone1, htone0, ltone1 and ltone0 as shown in table 14-5. table 14-5. dual tone frequency of cas and phase input data parameter values low tone frequency 2130hz 0.1% ltone1:0 4dfeh high tone frequency 2750hz 0.1% htone1:0 64b2h
s3c852b/P852B (p reliminary s pec ) caller id block 14- 15 fsk data generation tone generator is able to generate frequency shift keying (fsk) signal that satisfies all kinds of target specification and capable of producing the sequence of channel seizure, mark and data bytes only by setting fsk mode register (fskmod) and fsktd (fsk transmission data register), because it includes baud clock generator and fsk sequence generator. to generate fsk tone, the phase input data for space frequency must be written to htone1 and htone0, and the phase input values for mark frequency to ltone1 and ltone0. the frequency and phase input values of fsk are shown in table 14-6. table 14-6. fsk parameters specification space frequency htone1:0 mark frequency ltone1:0 bell202 2200 508eh 1200 2bf0h v.23 2100 4ce6 1300 2f9a v.21 1180 2b36 980 23e2 baud rate 1200 bps 1% the fsk generation function is enabled by setting tone enable bit (func register, bit 3) to "1" and fsk signal will be generated by setting fsk on-off bit (tones.0) to "1". in this case, dtononoff bit must be set to "0"; if fsk on-off is cleared to "0", fsk signal will not be generated. if the fsk generation fuction is on, the fsk sequence generator, shown in figure 14-20, automatically produces sequence of selection bit for mark and space frequency by baud rate. fsk sequence includes channel seizure, mark and fsk data, and fsk data is composed of 10-bit data including start bit (space), a byte of data and stop bit (mark) as shown in figure 14-5. basically, fsk sequence generator receives the data of fsktd and generates 10-bit fsk sequence by baud rate. when the mcu set fsk onoff bit to '1' after writing fsktd and fskmod, fsk sequence generator loads the data of fsktd and produces fsk transmission interrupt ( fsktint) while generating fsk sequence, so the mcu can write the next fsktd data and fskmod in the interrupt service routine. after finishing transmission of 10-bit data, the generator continuously loads the next fsktd and fskmod and produces fsktint to receive the next fsk data until the fsk generation function disabled. to generate channel seizure signal, clear mark enable ( markenable) bit (fskmod register, bit 0: it determines the value of start bit; '1': mark, '0': space) and write '55h' to fsktd register, then 10-bit sequence of channel seizure signal will be generated. to generate mark sequence, write 'ffh' to fsktd and set markenable bit to '1', then 10-bit of mark sequence will be generated. normal fsk data can be generated by clearing markenable bit to '0'. in this case, start (space) and stop (mark) bit will be attached to the head and tail of the data byte. if you don't change the contents of fsktd or fskmod after fsktint has occured, the tone generator generates previous fsk tone. after sending all fsk data successfully, set fskonoff bit to '0', and fsk sequence generation will be stopped after sending the last loaded data. if toneenable bit is cleared to '0', the tone generator stopped directly, so toneenable bit must be remained as '1' until sending sequence of the last data has been finished. to prevent loosing the last data due to toneenable bit reset, insert a dummy (no operation) interrupt routine after writing the last data and before clearing toneenable bit. the value of tonegh is the gain factor of fsk, because fsk uses high tone generator, note please disable all other interrupts except for fsktint while fsk sequence is generating to prevent the distortion of fsk sequencing time due to interrupt processing of other functions.
caller id blcok s3c852b/P852B (p reliminary s pec ) 14- 16 melody generator s3c852b contains dual frequency generator for providing melody generation. the high frequency generator is a musical scale (melody - tone1) generator, and the low frequency generator makes the length of the musical scale (rhythm - tone2). the tone1 generator provides 3 octaves 36 music scales, and the tone2 generator is able to control the rhythm with multiples of fx/2 15 (109.24hz) time scale. the frequencies of 3 octave music scale is shown in table 14-7. table 14-7. the frequencies and mref1 register values for 3 octave musical scale scale c3 c4 c5 freq. mref1 freq. mref1 freq. mref1 c 130.8 099h 261.6 135h 523.2 269h c# 138.9 0a3h 272.2 141h 554.3 28eh d 146.8 0ach 293.7 15ah 587.3 2b4h d# 155.5 0b6h 311.1 16fh 622.2 2deh e 164.8 0c1h 329.6 185h 659.2 309h f 174.6 0cdh 349.2 19ch 698.4 337h f# 185.0 0d9h 370.0 1b4h 739.9 368h g 196.0 0e6h 392.0 1ceh 783.9 39ch g# 207.6 0f3h 415.3 1eah 830.5 3d3h a 220.0 102h 440.0 207h 879.9 40dh a# 223.1 105h 466.2 20eh 932.2 44bh b 246.9 121h 493.9 246h 987.7 48ch the melody function can be enabled by mldenable bit (func register, bit 6). if mldenable bit is "1", the melody tone (mldt) is generated through mldo pin (#58). if mldenable bit is "0" the melody function is disabled and mldt and mldint will be stopped. as shown in table 14-9, tone1 (melody) can be generated by melody reference register mref1. when mref1 is set to 00h, the no melody tone is generated (mute). tone2 (rhythm) is generated by melody reference register mref2. the value of mref2 is the scale factor of fx/2 15 (109.24hz) duty cycle. tone2 pulse generates mldint interrupt. so user can program an interrupt service routine for melody generation. the routine is activated by mldint and user can write new mref1 and mref2 data to create new musical scale and length in the melody interrupt service routines. for example, to generate one-time, insert 52h into mref2 then the mldint will occure every 0.75 second.
s3c852b/P852B (p reliminary s pec ) caller id block 14- 17 the block diagram of melody generator is shown in figure 14-14. mref1 /2 /2 15 main clock (mclk ) counter value mref2 nco tone 1 clock mcnt2 tone 2 duty cycle compare logic pulse gen tone1 (to buzzer) pulse gen tone2 (to interrupt) counter reset 1 figure 14-14. block d iagram of m elody g enerator
caller id blcok s3c852b/P852B (p reliminary s pec ) 14- 18 power-down mode of cid block the cid block of the s3c852b can be put in power-down mode by programming the pdw bit in the mode register to "1". in this mode the input signal buffers, 14-bit adc?s, the reference bias generator of 14-bit adc, the tone generator and clock input from mcu are switched off. however the ring/line reversal detection can be active by programming the lrenable bit in the function register to be set. the serial interface can always be accessed, even in power-down mode. in power-down mode, if ring or line reversal occur when lrenable bit is "1", the lrint bit is set and an interrupt is generated. when the cid block of the s3c852b is put in power-down mode, all interrupt bits in the interrupt register of cid block cannot be set except for the lrint bit. the reset condition of cid block is power-down mode, that is, the default value of pwd bit is "1", so you should set the pwd bit to "0" to activate cid block. interrupt of cid block the cid interrupt ( int /p0.0) is active low. the flag in the interrupt register of cid block indicates the interrupt cause. interrupt flags of the cid block are set by hardware but must be reset by software. all flags of the interrupt register are reset when the register is read via the serial interface. the table 14-8 shows interrupt sources of the cid block. table 14-8. interrupt sources of the cid block source block generation ring/line reversal detector when lrstatus changes fsk receiver r eception of a new fsk data byte tone generator t ransmission of fsk data byte cas detector when casdetect changes sdt detector when sdtdetect changes melody generator when the duration (mref2) of current tone is expired
s3c852b/P852B (p reliminary s pec ) caller id block 14- 19 register maps of cid block the registers that are available in the cid block are shown in the following tables. table 14-9. register overview register n ame address function default v alue read/write mode 00h mode register 1000 0000 r ead/ w rite func 01h function register 0000 0000 r ead/ w rite tones 02h tone select register 0000 0000 r ead/ w rite gtime 0 a h guard time register 0000 0000 r ead/ w rite mref2 0bh melody generator duration control 0000 0000 r ead/ w rite mref1h 0ch melody generator reference register (high) 0000 0000 r ead/ w rite mref1l 0dh melody generator reference register (low) 0000 0000 r ead/ w rite intr 80h interrupt register 0000 0000 r ead/ w rite stat 81h status register 0000 0000 r ead o nly fskdt 82h fsk data register 0000 0000 r ead o nly htone1 87h msb of high tone register 0000 0000 r ead/ w rite htone0 88h lsb of high tone register 0000 0000 r ead/ w rite ltone1 89h msb of low tone register 0000 0000 r ead/ w rite ltone0 8ah lsb of low tone register 0000 0000 r ead/ w rite tonegh 90h high tone output gain control register 0000 0000 r ead/ w rite tonegl 91h low tone output gain control register 0000 0000 r ead/ w rite fsktd 92h fsk transmission data register 0000 0000 r ead/ w rite fskmod 93h fsk mode register 0000 0000 r ead/ w rite cont1 94h special control register1 0000 0000 r ead/ w rite cont2 95h special control register2 0000 0000 r ead/ w rite tmodsel 98h test mode selection register 0000 0000 r ead/ w rite casth 99h cas/sdt rejection level control register 0010 0011 r ead/ w rite
caller id blcok s3c852b/P852B (p reliminary s pec ) 14- 20 mode ? mode register address page 8 00h; read/write 7 6 5 4 3 2 1 0 pdw bomdc ? ? ? ? ? ? description of mode bits bit symbol description mode.7 pwd 1: puts the cid block in power-down mode 0: puts the cid block in active mode mode.6 bomdc 0: indicates that bomdetection bit is set to "1" after beginning of mark has been detected 1: indicates that bomdetection bit is set to "1" after channel seizure has been detected func ? function r egister address page 8 01h; read/write. 7 6 5 4 3 2 1 0 bfs mldenable sdtenable ? toneenable fskenable casenable lrenable description of func bits bit symbol description func.7 bfs 1: selects the single-ended input buffer 0: selects the differential input buffer func.6 mldenable 1: enables the melody generator 0: disables the melody generator func.5 sdtenable 1: enables the sdt detector 0: disables the sdt detector func.4 ? not used for s3c852b/P852B func.3 toneenable 1: enables the tone generator 0: disables the tone generator func.2 fskenable 1: enables fsk receiver 0: disables fsk receiver func.1 casenable 1: enables cas detector 0: disables cas detector func.0 lrenable 1: enables lr interrupts 0: disables lr interrupts
s3c852b/P852B (p reliminary s pec ) caller id block 14- 21 tones ? tone select register address page 8 02h; read/write. 7 6 5 4 3 2 1 0 ? ? ? ? ? ? dtononoff fskonoff description of tones bits bit symbol description tones.1 dtononoff 1: enables dual tone output 0: disables dual tone output tones.0 fskonoff 1: enables fsk tone output 0: disables fsk tone output gtime ? guard time register address page 8 0ah; read/write. 7 6 5 4 3 2 1 0 ? g6 g5 g4 g3 g2 g1 g0 description of gtime bits bit symbol description gtime.6 to gtime.0 g6 to g0 guard time to indicate the end of a line reversal or ring mref2 ? melody reference counter register2 adress page 8 0bh; read/write 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 description of mref2 bits bit symbol description mref2h.7 to mref2h.0 d7 to d0 the data of melody generator reference register 2
caller id blcok s3c852b/P852B (p reliminary s pec ) 14- 22 mref1h ?melody reference counter register1 (high byte) address page 8 0ch; read/write. 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 description of mref1h bits bit symbol description mref1h.7 to mref1h.0 d7 to d0 the data of melody frequency (high byte) mref1l ?melody reference counter register1 (low byte) address page 8 0dh; read/write. 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 description of mref1h bits bit symbol description mref1l.7 to mref1l.0 d7 to d0 the data of melody frequency (low byte)
s3c852b/P852B (p reliminary s pec ) caller id block 14- 23 intr ?interrupt register address page 8 80h; read/write. 7 6 5 4 3 2 1 0 mldint fsktint sdtint ? ? fskint casint lrint description of intr bits bit symbol description intr.7 mldint 1: indicates that the current melody tone duration has been finished intr.6 fsktint 1: indicates that previous fsk data transmission has been finished for fsk tone generation and is waiting for the next fsk data byte. intr.5 sdtint 1: indicates that sdtdetect has been changed and a sdt interrupt has occurred intr.4 not used for s3c852b/P852B intr.2 fskint 1: indicates that a new fsk data has been received intr.1 casint 1: indicates that cas signal has been detected intr.0 lrint 1: indicates that lrstatus has been changed and a lr interrupt has occurred. note: i ntr register is cleared by s/w by writing ?0?, but cannot write ?1? stat ?status register address page 8 81h; read only. 7 6 5 4 3 2 1 0 ? ? sdtdetect bomdetect ? ? casdetect lrstatus description of stat bits bit symbol description stat.5 sdtdetect 1: indicates that the sdt detector detects the signal that satisfies the specified frequency and energy level; 0: no more stutter dial tone is detected stat.4 bomdetect 1: indicates that the begin of the mark period during fsk reception has been detected stat.1 casdetect 1: indicates that a cas tone has been detected 0: no more cas tone is detected stat.0 lrstatus 1: lrint has not occurred until expiring gtime (reset value) 0: lrint has occurred before expiring gtime
caller id blcok s3c852b/P852B (p reliminary s pec ) 14- 24 fskdt ? fsk data register address page 8 82h; read only. 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 description of fskdt bits bit symbol description fskdt.7 to fskdt.0 d7 to d0 last received fsk data byte htone1 ? msb of high tone register address page 8 87h; read/write. 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 description of htone1 bits bit symbol description htone1.7 to htone1.0 d7 to d0 msb of 16-bit high tone register htone0 ? lsb of high tone register address page 8 88h; read/write. 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 description of htone0 bits bit symbol description htone0.7 to htone0.0 d7 to d0 lsb of 16-bit high tone register
s3c852b/P852B (p reliminary s pec ) caller id block 14- 25 ltone1 ? msb of low tone register address page 8 89h; read/write. 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 description of ltone1 bits bit symbol description ltone1.7 to ltone1.0 d7 to d0 msb of 16-bit low tone register ltone0 ? lsb of low tone register address page 8 8ah; read/write. 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 description of ltone0 bits bit symbol description ltone0.7 to ltone0.0 d7 to d0 lsb of 16-bit low tone register tonegh ? high tone output gain control register address page 8 90h; read/write 7 6 5 4 3 2 1 0 ? ? ? d4 d3 d2 d1 d0 description of tonegh bits bit symbol description tonegh.7 to tonegh.0 d7 to d0 this byte multiplied to control the output gain of tone generator
caller id blcok s3c852b/P852B (p reliminary s pec ) 14- 26 tonegl ? low tone output gain control register address page 8 91h; read/write 7 6 5 4 3 2 1 0 ? ? ? d4 d3 d2 d1 d0 description of tonegl bits bit symbol description tonegl.7 to tonegl.0 d7 to d0 this byte multiplied to control the output gain of tone generator fsktd ? fsk transmission data register address page 8 92h; read/write. 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 description of fsktd bits bit symbol description fsktd.7 to fsktd.0 d7 to d0 this byte is the fsk data to be transmitted. fskmod ? fsk mode register address page 8 93h; read only. 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? marken description of fskmod bits bit symbol description fskmod.0 marken 1: set fsk start bit to mark for mark sequence generation 0: set fsk start bit to space for normal fsk data generation
s3c852b/P852B (p reliminary s pec ) caller id block 14- 27 cont1 ? special control register address page 8 94h; read/write 7 6 5 4 3 2 1 0 1 1 0 0 0 1 1 1 this register should be written with "1100 0111b" cont2 ? special control register address page 8 95h; read/write 7 6 5 4 3 2 1 0 mclksel 0 0 0 0 0 0 0 this register should be written with "x000 0000b" description of cont2 bits bit symbol description cont2.7 mclksel 1: set mcu main clock to 7.15909mhz 0: set mcu main clock to 3.579545mhz tmodesel ? test mode selection register address page 8 98h; read/write 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 this register should be written with "0000 0000b" casth ? cas/sdt threshold control register address page 8 99h; read/write 7 6 5 4 3 2 1 0 0 0 1 0 0 0 1 1 this register should be written with "0011 0011b" notes 1. to allow for future extensions, reserved bits (indicated with "-") must be written with "0". 2. when reading from a register, the reserved bits (indicated with "-") return an undefined value (either "0" or "1").
caller id blcok s3c852b/P852B (p reliminary s pec ) 14- 28 notes
s3c852b/P852B (p reliminary s pec ) a/d converter 15- 1 15 a/d converter overview the 10-bit a/d converter (adc) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 10-bit digital values. the analog input level must lie between the av ref and av ss values. the a/d converter has the following components: ? analog comparator with successive approximation logic ? d/a converter logic (resistor string type) ? adc control register, adcon (set 1, bank 1, f4h, read/write, but adcon.3 is read only) ? four multiplexed analog data input pins (adc0?adc3) ? 10-bit a/d conversion data output register (addatah, addatal) ? internal av ref and av ss function description to initiate an analog-to-digital conversion procedure, at first, you must configure p1.0?p1.3 to analog input before a/d conversions because the p1.0 ? p1.3 pins can be used alternatively as normal data i/o or analog input pins. to do this, you load the appropriate value to the p1afs.0 ? p1afs.3 (for adc0 ? adc3) register. and you write the channel selection data in the a/d converter control register adcon to select one of the four analog input pins (adcn, n = 0?3) and set the conversion start or enable bit, adcon.0. an 10-bit conversion operation can be performed for only one analog input channel at a time. the read-write adcon register is located in set 1, bank 1 at address f4h. during a normal conversion, adc logic initially sets the successive approximation register to 200h (the approximate half-way point of an 10-bit register). this register is then updated automatically during each conversion step. the successive approximation block performs 10-bit conversions for one input channel at a time. you can dynamically select different channels by manipulating the channel selection bit value (adcon.5? 4) in the adcon register. to start the a/d conversion, you should set the enable bit, adcon.0. when a conversion is completed, acon.3, the end-of-conversion (eoc) bit is automatically set to 1 and the result is dumped into the addatah, addatal registers where it can be read. the adc module enters an idle state. remember to read the contents of addatah and addatal before another conversion starts. otherwise, the previous result will be overwritten by the next conversion result. note because the adc does not use sample-and-hold circuitry, it is important that any fluctuations in the analog level at the adc0?adc3 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to circuit noise, will invalidate the result.
a/d converter s3c85 2b/P852B (p reliminary s pec ) 15- 2 a/d converter control register (adcon) the a/d converter control register, adcon, is located in set1, bank 1 at address f4h. adcon is read-write addressable using 8-bit instructions only. but eoc bit, adcon.3 is read only. adcon has four functions: ? bits 5?4 select an analog input pin (adc0?adc3). ? bit 3 indicates the end of conversion status of the a/d conversion. ? bits 2?1 select a conversion speed. ? bit 0 starts the a/d conversion. only one analog input channel can be selected at a time. you can dynamically select any one of the four analog input pins, adc0?adc3 by manipulating the 2-bit value for adcon.5?adcon.4 start or enable bit 0 = disable operation 1 = start operation a/d converter control register (adcon) f4h, set 1, bank 1, r/w (adcon.3 bit is read-only) .7 .6 .5 .4 .3 .2 .1 .0 msb lsb end-of-conversion bit (realy only): 0 = conversion not complete 1 = conversion complete always logic zero a/d input pin selection bits: a/d input pin clock selection bit: .4 .5 0 1 0 1 0 0 1 1 adc0 adc1 adc2 adc3 conversion clock .1 .2 0 1 0 1 0 0 1 1 1/16 1/8 1/4 1/1 figure 15-1. a/d converter control register (adcon) .9 .8 .7 .6 .5 .4 .3 .2 lsb msb addatah (set 1, bank 1, f2h) - - - - - - .1 .0 lsb msb addatal (set 1, bank 1, f3h) figure 15-2. a/d converter data register (addatah/addatal)
s3c852b/P852B (p reliminary s pec ) a/d converter 15- 3 internal reference voltage levels in the adc function block, the analog input voltage level is compared to the reference voltage. the analog input level must remain within the range av ss to av ref (av ref = v dd ). different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first bit conversion is always 1/2 av ref . conversion result (adcdatah/adcdatal) + - to data bus to adcon.3 (eoc flag) successive approximation logic and register av ref av ss analog comparator 10-bit d/a converter m u x p1afs.0-.3 (select analog input function) adcon.0 (adc enable) adcon.0 (adc enable) p1.0/adc0 input pins p1.1/adc1 p1.2/adc2 p1.3/adc3 m u x 1/16 1/8 1/4 1/1 adcon.4-.5 (select one input pin of the assigned pins) adcon.2-.1 (select adc clock) notes: 1. adcon.0 will be "0" automatically when adc conversion is completed. 2. interval av ref only. 3. internal av ss only. fxx figure 15-3. a/d converter circuit diagram
a/d converter s3c85 2b/P852B (p reliminary s pec ) 15- 4 conversion timing the a/d conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up a/d conversion. therefore, total of 50 clocks are required to complete an 10-bit conversion: with an 10 mhz cpu clock frequency, one clock cycle is 400 ns (4/fxx). if each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 10-bits + step-up time (10 clock) = 50 clocks 50 clock x 400 ns = 20 m s at 10 mhz, 1 clock time = 4/fxx 50 adc clock adcon.0 1 . . . 40 clock previous value valid data set up time 10 clock addatah (8-bit) + addatal (2-bit) 9 8 7 6 5 4 3 2 1 0 conversion start eoc addata figure 15-4. a/d converter timing diagram
s3c852b/P852B (p reliminary s pec ) a/d converter 15- 5 internal a/d conversion procedure 1. analog input must remain between the voltage range of av ss and av ref . 2. configure p1.0?p1.3 for analog input before a/d conversions. to do this, you load the appropriate value to the p1afs.0?p1afs.3 (for adc0?adc3) register. 3. before the conversion operation starts, you must first select one of the four input pins (adc0?adc3) by writing the appropriate value to the adcon register. 4. when conversion has been completed, (50 clocks have elapsed), the eoc, adcon.3 flag is set to "1", so that a check can be made to verify that the conversion was successful. 5. the converted digital value is loaded to the output register, addatah (8-bit) and addatal (2-bit), than the adc module enters an idle state. 6. the digital conversion result can now be read from the addatah and addatal register. reference voltage input analog input pin note: the symbol "r" signifies an offset resistor with a value of from 50 to 100 w . v ss s3c852b adc0-adc3 av ref r v dd v dd 104 101 av ss figure 15-5. recommended a/d converter circuit for highest absolute accuracy
a/d converter s3c85 2b/P852B (p reliminary s pec ) 15- 6 f f programming tip ? configuring a/d converter ? ? sb0 ld p1afs,#00001111b ; p1.3?p1.0 a/d input mode ? ? sb1 ld adcon,#00000001b ; channel ad0: p1.0/conversion start ad0_chk: tm adcon,#00001000b ; a/d conversion end ? ? eoc check jr z,ad0_chk ; no ld ad0bufh,addatah ; 8-bit conversion data ld ad0bufl,addatal ; 2-bit conversion data sb0 ? ? sb1 ld adcon,#00110001b ; channel ad3: p1.3/conversion start ad6_chk: tm adcon,#00001000b ; a/d conversion end ? ? eoc check jr z,ad6_chk ; no ld ad6bufh,addatah ; 8-bit conversion data ld ad6bufl,addatal ; 2-bit conversion data sb0 ? ?
s3c852b/P852B (p reliminary s pec ) external interfac e 16- 1 16 external interface overview the s3c8 architecture supports accesses to memory and other peripheral devices over an external memory interface. both program and data memory areas can be accessed over the 16-bit address and an 8-bit data bus. instruction code can be fetched from external program memory. if external program memory is implemented in a ram-type device, you can write data to this memory space. the s3c852b has 100 pins in its qfp-type package, 80 of which are used for i/o. of these 80 pins, up to 28 can alternately be configured as external interface lines. the on-chip rom contains 64 k bytes of program memory. because the address bus carries 16-bit addresses, up to 64 k bytes of external memory space is supported. using the rom-less operating mode, you can configure up to 64 k bytes of program memory space externally. to configure the s3c852b to rom-less mode, you must first tie the ea pin to vdd. then, when a power-on reset occurs, the external interface lines at port 3, port 4, port 5 and port 6 are configured automatically. a 64-kbyte external data memory can also be implemented using the external peripheral interface. a data memory ( dm ) signal line (p3.1) selects data memory during external data accesses. dm output remains high level whenever instructions are being fetched or when the external program memory is being accessed. dm output goes active low when an external data memory location is addressed. to initialize the external interface, you must configure ports 3, 4, 5 and 6. port 4 pins are configured as data bus lines d0?d7 and port 5 pins are configured as address bus lines a0?a7. port 6 pins can be configured as needed to provide up to eight more address lines (a8?a15). the external program memory and data memory is controlled and selected by the program memory select signal ( pm ), the data memory signal ( dm ), the read signal ( rd ), and the write signal ( wr ). these select and control lines ( pm, dm, rd, wr ) are configured by bit settings in the port 3 alternative function select register, p3afs. the port 4, 5, 6 control registers, port 3 alternative function select register and two system registers are used to program the external interface. the two system registers are the system mode register, sym, and the external memory timing register, emt. sym.7 is the enable bit for the tri-state interface function. when tri-stating is enabled, the bus control lines of the external interface ?float? at high impedance. this feature is useful for applications requiring a shared external bus and for multiprocessor applications. emt register contains a control bit for selecting an external or internal stack area.
external interface s3c852b/P852B (p reliminary s pec ) 16- 2 s3c852b (top view) ea p3.0/ pm p3.1/ dm p3.2/ rd p3.3/ wr port 5, 6 external interface address lines (a5-a15) port 3 external interface signals 0 v = normal mode 5 v = rom-less mode p5.5/a5 p5.6/a6 p5.7/a7 p6.0/a8 p6.1/a9 p6.2/a10 p6.3/a11 p6.4/a12 p6.5/a13 p6.6/a14 p6.7/a15 p4.2/d2 p4.3/d3 p4.4/d4 p4.5/d5 p4.6/d6 p4.7/d7 p5.0/a0 p5.1/a1 p5.2/a2 p5.3/a3 p5.4/a4 p4.0/d0 p4.1/d1 port 4, 5 external interface address and data lines (a0-a4) and (d0-d7) figure 16-1. s3c852b external memory interface function diagram
s3c852b/P852B (p reliminary s pec ) external interfac e 16- 3 configuration options for external program memory program memory (rom) stores program code and table data. instructions can be fetched, or data read, from rom locations. the s3c852b has 64 k bytes internal mask-programmable rom (locations 0h?ffffh). also. using the external interface, it is possible to configure additional program memory space externally for applications. there are one way to configure external program memory: option 1: using the rom-less mode option, configure the entire 64-kbyte area (0000h?ffffh) externally. option 1: using rom-less mode to configure 64-kbytes of program memory externally option 1 will usually be chosen if external program memory is required. to configure the entire 64-kbyte rom address range externally, you must configure the s3c852b to operate in rom -less mode. this is done by applying 5 v to the ea pin (pin 19). you may recall that the s3c852b operates in normal (64-kbyte internal rom) mode when 0 v is applied to the ea pin. in rom-less mode, access to the internal rom is disabled. a reset automatically configures the external interface lines at ports 3, 4, 5 and 6. please note that the 5 v must be applied to the ea pin prior to reset and must remain at the 5-volt level during normal operation. you should not change the default settings in the port 3, 4, 5 and 6 control registers during normal operation. otherwise the external interface may be disabled. if you plan to implement option 1, the s3c852b?s internal 64-kbyte rom does not need to be mask- programmed. (decimal) 65,528 256 (hex) ffffh 0100h 0000h 0 interrupt vector area 64-kbyte external program memory area program start (decimal) 65,528 256 (hex) ffffh 0100h 0000h 0 interrupt vector area 64-kbyte internal program memory area program start internal rom mode external rom mode (normal operating mode, ea = 0 v) (rom-less operating mode, ea = 5 v) figure 16-2. internal and external program memory options
external interface s3c852b/P852B (p reliminary s pec ) 16- 4 external interface control registers the following registers are used to configure and control the external peripheral interface: ? system mode register, sym ? external memory timing register, emt ? port 3 alternative func tion select register, p3afs ? port 4 control register, p4con ? port 5 control register, p5con ? port 6 control register, p6con detailed descriptions of each of these registers can be found in part i, section 4, "control registers." system mode register (sym) the system mode register sym controls interrupt processing and also contains the enable bit (sym.7) for the 3- state external memory interface. sym is located in set 1 at address deh and can be read or written by 1-bit and 8-bit instructions. when 3-stating is enabled, the lines of the external memory interface 'float' in a high-impedance state. 3-stating is commonly used multiprocessing applications that require a shared external bus. not used .7 .6 .5 .4 .3 .2 .1 .0 lsb msb system mode register (sym) dfh, r/w global interrupt enable bit: 0 = disable all interrupts 1 = enable all interrupts fast interrupt enable bit: 0 = disable fast interrupts 1 = enable fast interrupts fast interrupt level selection bits: irq0 irq1 irq2 irq3 irq4 not used for s3c852b irq6 irq7 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 external interface tri-state enable bit: 0 = normal operation (tri-state disabled) 1 = high impedance (tri-state enabled) figure 16-3. system mode register (sym)
s3c852b/P852B (p reliminary s pec ) external interfac e 16- 5 external memory timing register (emt) the external memory timing register, emt, is used to control bus operations for external peripheral interface, including: ? stack area selection (external or internal area) .7 .6 .5 .4 .3 .2 .1 .0 lsb msb external memory timing control register (emt) feh, set 1, bank 0, r/w stack area selection bit: 0 = internal stack area 1 = external stack area not used not used figure 16-4. external memory timing control register (emt)
external interface s3c852b/P852B (p reliminary s pec ) 16- 6 port 3 alternative function select register (p3afs) the p3afs register is used to configure the port 3 pins, p3.0?p3.3, as control signal lines for the external interface. in normal operating mode a reset clears p3afs to ?00h?, configuring p3.0?p3.3 as normal i/o port. in rom-less mode, a reset automatically configures these pins as bus control lines. bit settings in the p3afs register activate p3.0?p3.3 as external memory control lines pm, dm, rd, wr , respectively. port 4 control register (p4con) the port 4 control register, p4con is used to configure the data lines d0?d7. in normal (internal rom) mode, a reset clears p4con to ?00h?, thereby configuring p4.0?p4.7 to schmitt trigger input mode. when using the s3c852b in rom-less mode, a reset automatically configures p4.0?p4.7 as data lines d0?d7, respectively. port 5 control register (p5con) the port 5 control register, p5con is used to configure the address lines a0?a7. in normal (internal rom) mode, a reset clears p5con to ?00h?, thereby configuring p5.0?p5.7 to schmitt trigger input mode. when using the s3c852b in rom-less mode, a reset automatically configures p5.0?p5.7 as address lines a0?a7, respectively. port 6 control register (p6con) the port 6 control register, p6con is used to configure the address lines a8?a15. in normal (internal rom) mode, a reset clears p6con to ?00h?, thereby configuring p6.0?p6.7 to schmitt trigger input mode. when using the s3c852b in rom-less mode, a reset automatically configures p6.0?p6.7 as address lines a8?a15, respectively. if you do not need all of the port 6 address lines for your application, you can use the remaining port 6 pins for general i/o. in this case, read operations will return valid port data only from the pins you configure for general i/o. table 16-1. control register overview for the external interface register location description sym deh, set 1 external tri-state interface enable bit (sym.7) emt feh, set 1, bank 0 external/internal stack selection control p3afs f2h, set 1, bank 0 select program memory signal ( pm ) at p3.0 select data memory signal ( dm ) at p3.1 enable read signal ( rd ) at p3.2 enable write signal ( wr ) at p3.3 p4con f3h, set 1, bank 0 configure data lines d0?d7 at p4.0?p4.7 p5con f4h, set 1, bank 0 configure address lines a0?a7 at p5.0?p5.7 p6con f5h, set 1, bank 0 configure address lines a8?a15 at p6.0?p6.7 note: when the s3c852b is used in rom-less mode (that is, when the ea pin is high level), a reset sets ports 3, 4, 5 and 6 to external interface pins. access to the internal rom is disable, and the entire 64-kbyte program memory address range is addressed externally over the external interface.
s3c852b/P852B (p reliminary s pec ) external interfac e 16- 7 table 16-2. external interface control register values after a reset reset (normal mode) register name mnemonic address bit values after reset (ea low) dec hex 7 6 5 4 3 2 1 0 system mode register sym 222 deh 0 ? ? x x x 0 0 port 3 alternative function select register p3afs 242 f2h ? ? ? ? 0 0 0 0 port 4 control register p4con 243 f3h 0 0 0 0 0 0 0 0 port 5 control register p5con 244 f4h 0 0 0 0 0 0 0 0 port 6 control register p6con 245 f5h 0 0 0 0 0 0 0 0 external memory timing register emt 254 feh ? 1 1 1 1 1 0 ? note : a dash (?) indicates that the bit is not used or not mapped; an 'x' means that the value is undefined after a reset. table 16-3. external interface control register values after a r r eset eset (rom-less mode) register name mnemonic address bit values after reset (ea high) dec hex 7 6 5 4 3 2 1 0 port 3 alternative function select register p3afs 242 f2h ? ? ? ? 1 1 1 1 note : in rom-less operating mode, a reset initializes all external interface control registers to their normal reset values, with the exception of p3afs. however, the external interface pins at port 4, port 5, port 6 and p3.0?p3.3 are internally configured to external interface mode.
external interface s3c852b/P852B (p reliminary s pec ) 16- 8 configuring separate external program and data memory areas you can address external program and data memory locations as a single combined space or as two separate spaces. if the program and data memory spaces are implemented separately, this separation is maintained logically using the data and program memory select signal ( dm and pm) . to select external data memory, you must set the bit 1 in the port3 alternative function select register, p3afs.1, to ?1?, because the p3afs.1 bit enable the dm output pin. the dm output is controlled automatically by hardware, that is, dm pin?s state goes active low to select the data memory area whenever one of the following instructions is executed: these instructions are used for accessing the external data and program memory. ? lde (load external data memory) ? lded (load external data memory and decrement) ? ldei (load external data memory and increment) ? ldepd (load external data memory with pre-decrement) ? l depi (load external data memory with pre-increment) if you set the stack area selection bit in the emt register, emt.1 to "1", the system stack area is configured externally. in this case, the dm signal will go active low whenever a call, pop, push, ret, or iret instruction is executed. using an external system stack the ks88 architecture supports stack operations in either the internal register file or in externally configured data memory. the push and pop instructions support external system stack operations. to select the external stack area option, you must set bit 1 in the external memory timing register (emt, feh) to "1". note the instruction you use to modify the stack selection bit in the emt register should not be immediately followed by an instruction that uses the stack. this could cause a program error. also, remember to disable interrupts by executing a di instruction before you modify the stack selection bit. a 16-bit stack pointer value (sph and spl) is required for external stack operations. after a reset, the sp values are undetermined. return addresses for procedure calls and interrupts, as well as dynamically generated data are stored on an externally-defined stack. the contents of the pc are saved on the external stack during a call instruction and restored by a ret instruction. when an interrupt occurs, the contents of the pc and the flags register are saved to the external stack. these values are then restored by an iret instruction.
s3c852b/P852B (p reliminary s pec ) external interfac e 16- 9 external bus operations the number of machine cycles that are required for external memory operations is two machine cycle. the notation used to describe basic timing periods in figures 16-5 to 16-12 are machine cycles ( mn), timing states ( tn), and clock periods. the clock wave form is shown for clarification only and does not have a specific timing relationship to the other signals. controlling external bus operations whenever the s3c852b/P852B external peripheral interface is active, the addresses of all internal program memory references will also appear on the external bus. this should have no effect on the external system, however, because the rd and wr signals are always high. ( rd and wr goes low only during external memory references.) shared bus feature the rd, wr, dm , pm signals, address, and data bus can be set to high impedance to enable the s3c852b/P852B to share common resources with other bus masters. this feature is often required for multiprocessor or related applications that require two or more devices that share the same external bus. the tri-state memory interface enable bit in the system mode register (sym.7) controls this function. when sym.7 = "1", the tri-state function is enabled, all external interface lines are set to high impedance, and the external bus is put under software control.
external interface s3c852b/P852B (p reliminary s pec ) 16- 10 t1 t2 t1 clock address data rd wr dm pm write cycle machine cycle (mn) t2 d0-d7 a0-a15 figure 16-5. external bus write cycle timing diagram (address, and data separated )
s3c852b/P852B (p reliminary s pec ) external interfac e 16- 11 t1 t2 t1 clock address data wr rd dm pm read cycle machine cycle (mn) t2 d0-d7 a0-a15 figure 16-6. external bus read cycle timing diagram
external interface s3c852b/P852B (p reliminary s pec ) 16- 12 table 16-4. s3c852b external memory interface signal descriptions signal name symbol pin active level description read rd 14 low rd determines the data transfer direction for external memory operations. write wr 15 low wr is low when writing to external program memory or data memory locations, and is high for all other operations. memory select dm 13 low when it is low, dm selects data memory. pm 12 low when it is low, pm selects program memory. note : if bit 7 of the sym register is high level, and assuming the external memory interface is configured, the rd, pm, wr, and dm signals, as well as address and data signal, will be set to high impedance state. this causes the external interface signals to 'float'.
s3c852b/P852B (p reliminary s pec ) external interfac e 16- 13 s3c852b ea v dd a8-a15 a0-a7 d0-d7 8 8 8 sram or equivalent eprom, eeprom or equivalent 8 8 8 a8-a15 a0-a7 d0-d7 a8-a15 a0-a7 d0-d7 we oe cs wr rd dm pm oe cs we figure 16-7. external interface function diagram (with sram and eprom or eeprom)
external interface s3c852b/P852B (p reliminary s pec ) 16- 14 s3c852b ea a8-a15 a0-a7 d0-d7 8 8 8 eprom, eeprom or equivalent a8-a15 a0-a7 d0-d7 rd oe ce v dd v dd we figure 16-8. external interface function diagram (external rom only)
s3c852b/P852B (p reliminary s pec ) external interfac e 16- 15 sam8 instruction execution timing diagrams t2 cpu clk address data wr rd t1 a0-a15 t2 t1 t2 t1 a0-a15 d0-d7 d0-d7 d0-d7 m1 m2 m1 fetch instruction fetch 1st byte of next instruction figure 16-9. external bus timing diagram for 1-byte fetch instructions t2 cpu clk address data wr rd t1 t2 t1 t2 t1 a0-a15 d0-d7 d0-d7 d0-d7 m1 m2 m1 a0-a15 a0-a15 fetch 1st byte fetch 2nd byte fetch 1st byte of next instruction figure 16-10. external bus timing diagram for 2-byte fetch instructions
external interface s3c852b/P852B (p reliminary s pec ) 16- 16 t2 cpu clk address data wr rd t1 t2 t1 t2 t1 a0-a15 d0-d7 d0-d7 d0-d7 m1 m2 m1 a0-a15 a0-a15 fetch 1st byte fetch 2nd byte fetch 3rd byte figure 16-11. external bus timing diagram for 3-byte fetch instructions t2 cpu clk address data wr rd t1 t2 t1 t2 t1 a0-a15 d0-d7 d0-d7 d0-d7 m1 m2 m1 a0-a15 a0-a15 t2 t1 m1 a0-a15 d0-d7 fetch 1st byte fetch 2nd byte fetch 3rd byte fetch 4th byte figure 16-12. external bus timing diagram for 4-byte fetch instructions
s3c852b/P852B (p reliminary s pec) electrical data 17- 1 17 electrical data overview in this chapter, s3c852b electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? d.c. electrical characteristics ? data retention supply vol tage in stop mode ? stop mode release timing when initiated by an external interrupt ? stop mode release timing when initiated by a reset ? i/o capacitance ? a.c. electrical characteristics ? input timing for external interrupts (port 0) ? input timing for reset ? oscillation characteristics ? oscillation stabilization time ? phase locked loop characteristics ? serial i/o timing characteristics ? a/d converter electrical characteristics ? analog circuit characteristics and consumed current ? electrical cha racteristics of cid block ? cas timing characteristics ? sdt timing characteristics ? serial interface timing characteristics ? oscillation stabilization time
electrical data s3c 852b/P852B (p reliminary s pec) 17- 2 table 17-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 7.0 v input voltage v in ports 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10 ? 0.3 to v dd + 0.3 v output voltage v o all output pins ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 18 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 ma total pin current for ports 0, 1, and 3?10 + 100 total pin current for port 2 + 40 operating temperature t a ? 0 to + 70 c storage temperature t stg ? ? 10 to + 100 c
s3c852b/P852B (p reliminary s pec) electrical data 17- 3 table 17-2. d.c. electrical characteristics (t a = 0 c to + 70 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage v dd fx = 3.579545 mhz (instruction clock=0.89 mhz) (note) 2.7 ? 5.5 v input high voltage v ih1 all input pins except v ih2 and v ih3 0.8 v dd ? v dd v ih2 reset 0.7 v dd v dd v ih3 x in , xt in v dd ? 0.3 v dd input low voltage v il1 all input pins except v il2 and v il3 0 ? 0.2 v dd v il2 reset 0 ? 0.3 v dd v il3 x out , xt out 0.3 output high voltage v oh v dd = 4.5 to 6.0 v; i oh = ? 1 ma ports 0 - 6 v dd ? 1.0 ? ? v i oh = ? 100 ua v dd ? 0.5 output low voltage v ol1 v dd = 4.5 to 6.0 v; i ol = 2 ma, all output pins except v ol2 ? 0.4 2.0 v ol2 v dd = 4.5 to 6.0 v; i ol = 15 ma, ports 2 0.4 2.0 input high leakage current i lih1 v in = v dd ; all input pins except x in , x out , xt in , and xt out ? ? 1 m a i lih2 v in = v dd ; x in , x out , xt in , and xt out 20 input low leakage current i lil1 v in = 0 v; all input pins except reset , x in , x out , xt in , and xt out ? ? ? 1 i lil2 v in = 0 v; x in , x out , xt in , and xt out ? 20 output high leakage current i loh v out = v dd ;all output pins ? ? 1 output low leakage current i lol v out = 0 v ;all output pins ? ? ? 1 pull-up resistors r l1 v in =0 v; t a =25 c; v dd =5.0 v ports 0 ? 10 25 47 100 k w v dd =3.0 v 50 90 150 r l2 v in =0 v; t a =25 c; v dd =5.0 v reset only 150 250 350 v dd =3.0 v 300 500 700 note: minimum instruction clock.
electrical data s3c 852b/P852B (p reliminary s pec) 17- 4 table 17-2. d.c. electrical characteristics (continued) (t a = 0 c to + 70 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit supply current (note) i dd1 v dd = 5.0 v 10% crystal oscillator 3.58mhz ? 4.0 8.0 ma c1 = c2 = 22pf v dd = 3.0 v 10% 3.58mhz ? 2.0 4.0 i dd1cid v dd = 5.0 v 10% crystal oscillator 3.58mhz ? 8.0 16.0 ma c1 = c2 = 22pf v dd = 3.0 v 10% 3.58mhz ? 4.0 8.0 i dd2 v dd = 5.0 v 10% crystal oscillator 3.58mhz ? 2.5 4.6- ma c1 = c2 = 22pf v dd = 3.0 v 10% 3.58mhz ? 0.8 1.6 i dd3 v dd = 3.0 v 10%, 32.768 khz c1 = c2 = 22pf ? 20 40 m a i dd4 v dd = 3.0 v 10%, 32.768 khz c1 = c2 = 22pf ? 10 20 i dd5 stop mode; v dd =5.0v 10%, osccon.2=1 ? 0.5 5 v dd =3.0v 10%, 0.2 2 notes: 1. supply current does not include current drawn through internal pull-up resistors, adc or external output current loads. 2. i dd1 , i dd2 , i dd3 and i dd4 include power consumption for subsystem clock oscillation. 3. i dd3 is the supply current when cas signal is receiving 4. every values in this table is measured when bits 4-3 of the system clock control register (clkcon.4-.3) is set to 11b. 5. i dd5 is current when bit2 of the oscillator control register (osccon.2) is set to logic 1.
s3c852b/P852B (p reliminary s pec) electrical data 17- 5 table 17-3. data retention supply voltage in stop mode (t a = 0 c to + 70 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.0 ? 6.0 v data retention supply current i dddr stop mode,v dddr =1.0 v ? ? 1 m a oscillator stabilization wait time t wait released by reset ? 2 16 /fx (1) ? ms released by interrupt ? (2) ? notes: 1. fx is the main oscillator frequency. 2. the duration of the oscillation stabilization time (t wait ) when it is released by an interrupt is determined by the setting in the basic timer control register, btcon. execution of stop instruction idle mode (basic timer active) ~ ~ v dddr ~ ~ stop mode normal operating mode data retention mode interrupt request v dd 0.8 v dd t wait figure 17-1. stop mode release timing when initiated by an external interrupt
electrical data s3c 852b/P852B (p reliminary s pec) 17- 6 execution of stop instrction reset occurs ~ ~ v dddr ~ ~ stop mode oscillation stabilization time normal operating mode data retention mode t wait reset v dd 0.2 v dd 0.8 v dd t srl figure 17-2. stop mode release timing when initiated by a reset reset
s3c852b/P852B (p reliminary s pec) electrical data 17- 7 table 17-4. input/output capacitance (t a = 0 c to + 70 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io table 17-5. a.c. electrical characteristics (t a = 0 c to + 70 c) parameter symbol conditions min typ max unit interrupt input, high, low width t inth , t intl p0.1 ? p0.7 v dd = 5 v 150 200 ? ns reset input low width t rsl input v dd = 5 v 1000 ? 10000 t inth t intl 0.8 v dd 0.2 v dd note: the unit t cpu means one cpu clock period. external interrupt figure 17-3. input timing for external interrupts (p0.0?p0.7) reset t rsl 0.3 v dd figure 17-4. input timing for reset reset
electrical data s3c 852b/P852B (p reliminary s pec) 17- 8 table 17-6. main oscillation characteristics (t a = 0 c to + 70 c, v dd = 2.7 v to 5.5 v) oscillator clock circuit conditions min typ max unit crystal oscillator x in x out c2 c1 cpu clock oscillation frequency v dd = 2.2 v to 6.0 v ? 3.579545 ? mhz external clock x in x out x in input frequency v dd = 2.2 v to 6.0 v ? 3.579545 ? table 17-7. sub oscillation characteristics (t a = 0 c to + 70 c, v dd = 2.7 v to 5.5 v) oscillator clock circuit conditions min typ max unit crystal oscillator xt in xt out c2 c1 cpu clock oscillation frequency 32 32.768 35 khz external clock xt in xt out xt in input frequency 32 ? 100 khz
s3c852b/P852B (p reliminary s pec) electrical data 17- 9 table 17-8. main oscillation stabilization time (t a = 0 c to + 70 c) oscillator test condition min typ max unit crystal v dd = 4.5 v to 6.0 v ? ? 10 ms oscillator v dd = 2.0 v to 4.5 v ? ? 30 ceramic oscillator oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms external clock x in input high and low width (t xh , t xl ) 62.0 ? 1250 ns t xh t xl v dd -0.5 v 0.5 v x in 1/fx figure 17-5. clock timing measurement at x in table 17-9. sub oscillation stabilization time (t a = 0 c to + 70 c, v dd = 3.0 v 10 %) oscillator test condition min typ max unit crystal v dd = 4.5 v to 6.0 v ? 1.0 2 s v dd = 2.0 v to 4.5 v ? ? 10 external clock x in input high and low width (t xh , t xl ) 5 ? 15 m s t xth t xtl v dd -0.5 v 0.5 v xt in 1/fxt figure 17-6. clock timing measurement at xt in
electrical data s3c 852b/P852B (p reliminary s pec) 17- 10 table 17-10. phase locked loop characteristics (t a = 0 c to + 70 c, v dd = 2.7 v to 5.5v, x tin = 32.768khz 0.05%, x in = 3.579545mhz, c pllc = 0.1 m f) parameter test condition min typ max unit operating voltage t a = 0 c to + 70 4.5 ? 5.5 v output frequency v dd = 2.7 v to 5.5 v main clock (fx) generation 3.579 3.579545 3.58 main clock doubling (fx*2) 7.158 7.15909 7.160 stabilization time v dd = 2.7 v to 5.5 v main clock (fx) generation ? ? 0.5 s
s3c852b/P852B (p reliminary s pec) electrical data 17- 11 table 17-11. serial i/o timing characteristics (t a = 0 c to + 70 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit sck cycle time t cky external sck source 1000 ? ? ns internal sck source 1000 sck high, low width t kh , t kl external sck source 500 ? ? internal sck source t kcy /2 ? 50 si setup time to sck low t sik external sck source 250 ? ? internal sck source 250 si hold time to sck high t ksi external sck source 400 ? ? internal sck source 400 output delay for sck to so t kso external sck source ? ? 300 internal sck source 250 note : " sck " means serial i/o clock frequency, "si" means serial data input, and "so" means serial data output. output data input data sck t kh t kcy t kl 0.8 v dd 0.2 v dd t kso t s k t ksi 0.8 v dd 0.2 v dd si so figure 17-7. serial data transfer timing
electrical data s3c 852b/P852B (p reliminary s pec) 17- 12 table 17-12. a/d converter electrical characteristics ( t a = 0 c to + 70 c, v dd = 2.7 v to 5.5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution 10 10 10 bit absolute accuracy (1) v dd = 5.12 v fx = 8 mhz av ref = (10/10)v dd av ss = 0 v ? ? | 3 | lsb conversion time (2) t con conversion clock = fx (3) 50/fx ? ? us analog reference voltage av ref ? v dd - 0.1 v dd v dd + 0.1 v analog ground av ss ? v ss ? ? v analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 ? ? m w notes: 1. excluding quantization error, absolute accuracy equals 1/2 lsb. 2. 'conversion time' is the time required from the moment a conversion operation starts until it ends. 3. the conversion clock is selected by bits 2-1 of a/d converter control register, adcon.2-.1.
s3c852b/P852B (p reliminary s pec) electrical data 17- 13 table 17-13. electrical c haracteristics of cid block ( r eceiver & d etectors) ( t a = 0 c to + 70 c, v dd = 5.0 v 5 %, x in = 3.579545mhz 0.1% ) symbol parameter min typ max unit voltage reference v ref reference voltage output 2.25 v cas detector thac input accept threshold (in 600 w load ) -38 dbm pic input signal power ( in 600 w load ) -37 0 dbm flc low tone frequency 2130 hz fhc high tone frequency 2750 hz d fmaxc maximum frequency deviation -0.6 +0.6 % t wc twist -6 6 db fsk receiver pif input signal power ( in 600 w load ) -42 0 dbm fd data transmission rate frequency 1188 1200 1212 baud fmb mark frequency (bell202) 1188 1200 1212 hz fsb space frequency (bell202) 2178 2200 2222 hz fmv mark frequency (ccitt/v23) 1300 hz fsv space frequency (ccitt/v23) 2100 hz twf twist -10 10 db s/n0 signal to noise ratio (0hz ? 200hz) -25 db s/n1 signal to noise ratio (200hz ? 3.2khz) 6 db s/n3 signal to noise ratio (3.2khz ? 15khz) -25 db sdt detector fls low tone frequency 350 hz fhs high tone frequency 440 hz tws twist -6 +6 db thap input accept threshold (in 600 w load ) -38 -5 dbm
electrical data s3c 852b/P852B (p reliminary s pec) 17- 14 table 17-14. cas t iming c haracteristics ( t a = 0 c + 70 c , v dd = 2.7 v to 5.5 v, x in = 3.579545mhz 0.1% ) parameter symbol min typ max unit cas detection time from cas start t detc 67 ms detection off time from cas end t offc 30 ms cas detection time width t widthc 8 ms table 17-15. electrical c haracteristics of cid block ( t one g enerator) ( t a = 25 c, v dd = 5.0 v 5% (max), 3.3v 5% (typ), x in = 3.579545mhz 0.1% high & low tone gain = 10h, r11 = 9k w , c8 = 2.2nf, terminal impedence = 600 w ) symbol parameter min typ max unit dtmf g eneration pod output signal power (for high tone) ? -4.3 0.4 dbm d fmaxd_g maximum frequency deviation -0.1 +0.1 % s/nd signal to noise ratio (0 ? 6khz) -32 dbv fsk g eneration pof output signal power (for high tone) ? -4.3 0.2 dbm d fmaxf_g maximum frequency deviation -0.1 +0.1 % s/nf signal to noise ratio (0 ? 6khz) -45 dbv cas g eneration poc output signal power (for high tone) ? -5.3 -0.2 dbm d fmaxc_g maximum frequency deviation -0.1 +0.1 % s/nc signal to noise ratio (0 ? 6khz) -34 dbv line signal t detc casdet t widthc int cas signal t offc figure 17-8. waveform for cas timing characteristics
s3c852b/P852B (p reliminary s pec) electrical data 17- 15 table 17-16. sdt t iming c haracteristics ( t a = 0 c + 70 c , v dd = 2.7 v to 5.5 v x in = 3.579545mhz 0.1% ) parameter symbol min typ max unit sdt detection time from sdt start t dets 60 ms detection off time from sdt end t offc 30 ms line signal t dets sdtdet int sdt signal t offs figure 17-9. waveform for sdt timing characteristics
electrical data s3c 852b/P852B (p reliminary s pec) 17- 16 notes
s3c852b/P852B (p reliminary s pec ) mechanical data 18- 1 18 mechanical data overview the s3c852b microcontroller is currently available in a 100-pin qfp package.
mechanical data s3c 852b/P852B (p reliminary s pec ) 18- 2 #100 note : dimensions are in millimeters. #1 0.65bsc 0.30 0.08 0.15 max (0.58) 20.00 0.20 23.90 0.30 14.00 0.20 17.90 0.30 0.10 max 0.15 0-8 0.80 - 0.20 0.05min 2.65 3.00 max 0.10 + 0.10 - 0.05 100-qfp-1420c figure 18-1. 100-pin qfp package mechanical data
s3c852b/P852B (p reliminary s pec ) s3P852B otp 19- 1 19 s3P852B otp overview the s3P852B single-chip cmos microcontroller is the otp (one time programmable) version of the s3c852b microcontroller. it has an on-chip otp rom instead of a masked rom. the eprom is accessed by serial data format. the s3P852B is fully compatible with the s3c852b, both in function in d.c. electrical characteristics, bonding information and in pin configuration. because of its simple programming requirements, the s3P852B is ideal as an evaluation chip for the s3c852b.
s3P852B otp s3c852b/p 852b (p reliminary s pec ) 19- 2 p5.7/a7 p5.6/a6 p5.5/a5 p5.4/a4 p5.3/a3 p5.2/a2 p5.1/a1 p5.0/a0 p4.7/d7 p4.6/d6 p4.5/d5 p4.4/d4 p4.3/d3 p4.2/d2 p4.1/d1 p4.0/d0 p3.3/ wr p3.2/ rd p3.1/ dm p3.0/ pm p7.7 p7.6 p7.5 p7.4 p7.3 p0.7/int7 p0.6/int6/tb p0.5/int5/ta p0.4/int4/t1ck p0.3/int3/t0/t0cap p2.0 p2.1 p2.2(sdat) p2.3(sclk) v dd v ss x out x in ea xt in xt out reset p0.0/int0 p0.1/int1/buz p0.2/int2/t0ck p9.7 p9.6 p9.5 p9.4 p9.3 s3c852b/P852B 100-qfp-1420c 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 p8.7 p8.6 p8.5 p8.4 p8.3 p8.2 p8.1 p8.0 pllc cksel p7.2 p7.1 p7.0 vdda inp inn out ins v ref toneo vssa lr in mldo p10.7 p10.6 p10.5 p10.4 p10.3 p10.2 p10.1 p10.0 p6.7/a15 p6.6/a14 p6.5/a13 p6.4/a12 p6.3/a11 p6.2/a10 p6.1/a9 p6.0/a8 p1.7/ssd/sd3 p1.6/ sck /sd2 p1.5/so/sd1 p1.4/si/sd0 p1.3/adc3 p1.2/adc2 p1.1/adc1 p1.0/adc0 p9.0 p9.1 p9.2 figure 19-1. s3P852B pin assignments (100-pin qfp package)
s3c852b/P852B (p reliminary s pec ) s3P852B otp 19- 3 table 19-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p2.2 sdat 13 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p2.3 sclk 14 i serial clock pin. input only pin. ea v pp 19 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is aplied, otp is in reading mode. (option) reset reset 22 i chip initialization v dd /v ss v dd /v ss 15/16 ? logic power supply pin. v dd should be tied to +5 v during programming. table 19-2. comparison of s3P852B and s3c852b features characteristic s3P852B s3c852b program memory 64-kbyte eprom 64-kbyte mask rom operating voltage (v dd ) 2.7 v to 5.5 v 2.7 v to 5.5 v otp programming mode v dd = 5 v, v pp (ea) = 12.5 v pin configuration 100 qfp 100 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (ea) pin of the s3P852B, the eprom programming mode is entered.
s3P852B otp s3c852b/p 852b (p reliminary s pec ) 19- 4 notes
(for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) s3c8- series mask rom order form product description: device number: s3c852b_ _- ___________(write down the rom code number) product order form: package pellet wafer package type: __________ package marking (check one): standard custom a custom b (max 10 chars) (max 10 chars each line) @ : assembly site code, y : last number of assembly year, ww : week of assembly @ yww device name sec device name @ yww @ yww delivery dates and quantities: deliverable required delivery date quantity comments rom code ? not applicable see rom selection form customer sample risk order see risk order sheet please answer the following questions: f f for what kind of product will you be using this order? new model upgrade of an existing model replacement of an existing model others if you are replacing an existing model, please indicate the former product name ( ) f f what are the main reasons you decided to use a samsung microcontroller in your product? please check all that apply. price product quality features and functions development system technical support delivery on time used same mcu before quality of documentation samsung reputation mask charge (us$ / won): ____________________________ customer information: company name: ___________________ telephone number _________________________ signatures: ________________________ __________________________________ (person placing the order) (technical manager)

(for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) s3c8- series request for production at customer risk customer information: company name: ________________________________________________________ ________ department: ________________________________________________________________ telephone number: __________________________ fax: _____________________________ date: __________________________ risk order information: device number: s3c852b___- ________ (write down the rom code number) package: number of pins: ____________ package type: _____________________ intended application: ________________________________________________________________ product model number: __________________________________ ______________________________ customer risk order agreement: we hereby request sec to produce the above named product in the quantity stated below. we believe our risk order product to be in full compliance with all sec production specifications and, to this extent, agree to assume responsibility for any and all production risks involved. order quantity and delivery schedule: risk order quantity: _____________________ pcs delivery schedule: delivery date (s) quantity comments signatures: _______________________________ _________________________________ ______ (person placing the risk order) (sec sales representative)

(for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) s3c852b mask option selection form device number: s3c852b___-________(write down the rom code number) attachment (check one): diskette prom customer checksum: ________________________________________________________________ company name: __________________________________________________ ______________ signature (engineer): ________________________________________________________________ please answer the following questions: f f application (product model id: _______________________) audio video telecom lcd databank caller id lcd game industrials home appliance office automation remocon other please describe in detail its application

(for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) s3p8- series otp mcu factory writing order form (1/2) product description: device number: s3P852B___-________(write down the rom code number) product order form: package pellet wafer if the product order form is package: package type: _____________________ package marking (check one): standard custom a custom b (max 10 chars) (max 10 chars each line) @ : assembly site code, y : last number of assembly year, ww : week of assembly @ yww device name sec device name @ yww @ yww delivery dates and quantity: rom code release date required delivery date of device quantity please answer the following questions: f f what is the purpose of this order? new product development upgrade of an existing product replacement of an existing microcontroller others if you are replacing an existing microcontroller, please indicate the former microcontroller name ( ) f f what are the main reasons you decided to use a samsung microcontroller in your product? please check all that apply. price product quality features and functions development system technical support delivery on time used same mcu before quality of documentation samsung reputation customer information: company name: ___________________ telephone number _________________________ signatures: ________________________ __________________________________ (p erson placing the order) (technical manager)

(for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) s3P852B otp mcu factory writing order form (2/2) device number: s3P852B ___-__________ (write down the rom code number) customer checksums: _______________________________________________________________ company name: ________________________________________________________________ signature (engineer): ________________________________________________________________ read protection (1) : yes no please answer the following questions: f f are you going to continue ordering this device? yes no if so, how much will you be ordering? _________________ pcs f f application (product model id: _______________________) audio video telecom lcd databank caller id lcd game industrials home appliance office automation remocon other please describe in detail its application ___________________________________________________________________________ notes 1. once you choose a read protection, you cannot read again the programming code from the eprom. 2. otp mcu writing will be executed in our manufacturing site. 3. the writing program is completely verified by a customer. samsung does not take on any responsibility for errors occurred from the writing program.

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